soc/intel/broadwell: Add back support for EHCI debug setup

The EHCI debug device setup code was removed from broadwell in
commit 49ee5ef: http://review.coreboot.org/11874

However the generic device setup code is in the southbridge/common/intel
directory while broadwell is in the soc directory so this is not used.
Add it back to the broadwell soc to fix undefined reference compile
errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'.

This was tested to compile and produce romstage and ramstage output on a
google/samus board.

Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/soc/intel/broadwell/Makefile.inc

@@ -60,6 +60,8 @@ ramstage-y += systemagent.c
 ramstage-y += tsc_freq.c
 romstage-y += tsc_freq.c
 smm-y      += tsc_freq.c
+romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
 ramstage-y += ehci.c
 ramstage-y += xhci.c
 smm-y      += xhci.c

src/soc/intel/broadwell/usb_debug.c

@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ehci.h>
+#include <device/pci_def.h>
+
+pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+	u32 class;
+	pci_devfn_t dev = PCI_DEV(0, 0x1d, 0);
+
+	class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
+	if (class != PCI_EHCI_CLASSCODE)
+		return 0;
+
+	return dev;
+}
+
+void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
+{
+	/* Hardcoded to physical port 1 */
+}
+
+void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
+{
+	u32 tmp32;
+
+	if (!dev)
+		return;
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, base);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+	/* Force ownership of hte Debug Port to the EHCI controller. */
+	tmp32 = read32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET));
+	tmp32 |= (1 << 30);
+	write32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET), tmp32);
+}