soc/amd/sabrina/acpi: Correct VID decoding on Sabrina

Sabrina uses the SVI3 spec for VID tables which is incompatible with the
SVI2 spec used on PCO/CZN. Move the defines from common to soc and
update the decoding for sabrina.

See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables

TEST=timeless builds on mandolin/majolica for PCO/CZN
     build chausie and verify pstate power is correct in ACPI tables

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I915e962f11615246690c6be1bee3533336a808f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/include/cpu/amd/msr.h

@@ -44,9 +44,6 @@
 #define PSTATE_2_MSR			0xC0010066
 #define PSTATE_3_MSR			0xC0010067
 #define PSTATE_4_MSR			0xC0010068
-/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
-#define  SERIAL_VID_DECODE_MICROVOLTS	6250
-#define  SERIAL_VID_MAX_MICROVOLTS	1550000L
 #define MSR_PATCH_LOADER		0xC0010020
 
 #define MSR_COFVID_STS			0xC0010071

src/soc/amd/cezanne/include/soc/msr.h

@@ -21,6 +21,10 @@
 #define PSTATE_DEF_LO_FREQ_MUL_MASK	(0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
 #define PSTATE_DEF_LO_CORE_FREQ_BASE	25
 
+/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
+#define  SERIAL_VID_DECODE_MICROVOLTS	6250
+#define  SERIAL_VID_MAX_MICROVOLTS	1550000L
+
 #define MSR_CPPC_CAPABILITY_1				0xc00102b0
 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16

src/soc/amd/picasso/include/soc/msr.h

@@ -25,4 +25,8 @@
 #define PSTATE_DEF_LO_FREQ_MUL_MASK	(0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
 #define PSTATE_DEF_LO_CORE_FREQ_BASE	25
 
+/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
+#define  SERIAL_VID_DECODE_MICROVOLTS	6250
+#define  SERIAL_VID_MAX_MICROVOLTS	1550000L
+
 #endif /* AMD_PICASSO_MSR_H */

src/soc/amd/sabrina/acpi.c

@@ -187,12 +187,12 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
 		(pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT;
 
 	/* Voltage */
-	if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) {
+	if (core_vid == 0x00) {
-		/* Voltage off for VID codes 0xF8 to 0xFF */
+		/* Voltage off for VID code 0x00 */
 		voltage_in_uvolts = 0;
 	} else {
 		voltage_in_uvolts =
-			SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
+			SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
 	}
 
 	/* Power in mW */

src/soc/amd/sabrina/include/soc/msr.h

@@ -21,6 +21,10 @@
 #define PSTATE_DEF_LO_FREQ_MUL_MASK	(0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
 #define PSTATE_DEF_LO_CORE_FREQ_BASE	25
 
+/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
+#define  SERIAL_VID_DECODE_MICROVOLTS	5000
+#define  SERIAL_VID_BASE_MICROVOLTS	245000L
+
 #define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
 #define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8