Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster"
in device trees. Adapt sconfig as necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
68befd5d34
commit
8d313685b0
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@ -1,7 +1,7 @@
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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@ -1,7 +1,7 @@
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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@ -1,7 +1,7 @@
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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@ -59,9 +59,9 @@ chip northbridge/amd/lx
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end
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end
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# APIC cluster is late CPU init.
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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device lapic 0 on end
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end
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end
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end
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@ -9,9 +9,9 @@
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#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
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#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_S1G1
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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@ -9,9 +9,9 @@
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#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
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#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_AM2
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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@ -1,8 +1,8 @@
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# sample config for amd/mahogany_fam10
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chip northbridge/amd/amdfam10/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_AM2r2 #L1 and DDR2
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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@ -32,9 +32,9 @@ chip northbridge/amd/lx
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end
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end
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# APIC cluster is late CPU init.
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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device lapic 0 on end
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end
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end
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end
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@ -9,9 +9,9 @@
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#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
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#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_AM2
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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@ -1,9 +1,9 @@
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chip northbridge/amd/gx2
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register "setupflash" = "0"
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#register "irqmap" = "0xaa5b"
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/model_gx2
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_F
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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@ -1,7 +1,7 @@
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chip northbridge/amd/amdfam10/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_F_1207 #L1 and DDR2
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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@ -1,8 +1,8 @@
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# sample config for amd/tilapia_fam10
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chip northbridge/amd/amdfam10/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_AM3 #L1 and DDR3
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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@ -32,9 +32,9 @@ chip northbridge/amd/lx
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end
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end
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# APIC cluster is late CPU init.
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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device lapic 0 on end
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end
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end
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#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
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#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_939
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8/root_complex # Root complex
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_939 # Socket 939 CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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chip northbridge/amd/amdk8/root_complex # Root complex
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_939 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8/root_complex # Root complex
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_AM2 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/intel/i82810 # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/socket_PGA370 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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chip cpu/intel/slot_1 # CPU
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device apic 1 on end # APIC
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device lapic 1 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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chip cpu/intel/slot_1 # CPU
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device apic 1 on end # APIC
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device lapic 1 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 12.0 on end # Ethernet
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end
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end
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/via/model_c7 # VIA C7
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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end
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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@ -58,12 +58,12 @@ chip northbridge/intel/e7520 # mch
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device pci 04.0 on end
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device pci 06.0 on end
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end
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/intel/socket_mPGA604 # cpu 0
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device apic 0 on end
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device lapic 0 on end
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end
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chip cpu/intel/socket_mPGA604 # cpu 1
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device apic 6 on end
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device lapic 6 on end
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end
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end
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register "intrline" = "0x00070100"
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end
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end
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end
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/intel/socket_mPGA479M
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device apic 0 on end
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device lapic 0 on end
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end
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end
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end
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@ -76,9 +76,9 @@ chip northbridge/amd/lx
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end
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# APIC cluster is late CPU init.
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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device lapic 0 on end
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end
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end
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_AM2
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_AM2
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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@ -1,7 +1,7 @@
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_F
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device apic 0 on end
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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# TODO: i810E actually!
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chip northbridge/intel/i82810 # Northbridge
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device apic_cluster 0 on # APIC cluster
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/socket_PGA370 # CPU
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device apic 0 on end # APIC
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on
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@ -69,12 +69,12 @@ chip northbridge/amd/amdk8/root_complex
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device pci 19.3 on end
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end
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end
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
|
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device lapic 0 on end
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end
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chip cpu/amd/socket_940
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device apic 1 on end
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device lapic 1 on end
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end
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end
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end
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@ -1,7 +1,7 @@
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device lapic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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||||
device lapic 0 on end
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end
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end
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|
|
@ -67,9 +67,9 @@ chip northbridge/amd/lx
|
|||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -19,9 +19,9 @@
|
|||
|
||||
chip northbridge/intel/i945
|
||||
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_441
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
@ -64,9 +64,9 @@ chip northbridge/intel/i3100
|
|||
device pci 1f.4 on end # Performance counters
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/bga956
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -68,12 +68,12 @@ chip northbridge/intel/e7520
|
|||
register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu 0
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # cpu 1
|
||||
device apic 6 on end
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -36,9 +36,9 @@ chip northbridge/intel/i3100
|
|||
device pci 1f.3 on end # SMBus
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA479M
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -46,9 +46,9 @@ chip northbridge/intel/i3100
|
|||
device pci 1f.4 on end # ?
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/ep80579
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -61,12 +61,12 @@ chip northbridge/intel/e7501
|
|||
device pci 1f.6 off end # AC97 Modem
|
||||
end # SB
|
||||
end # PCI_DOMAIN
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604
|
||||
device apic 6 on end
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -77,12 +77,12 @@ chip northbridge/amd/amdk8/root_complex
|
|||
device pci 19.3 on end
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/amd/socket_940
|
||||
device apic 1 on end
|
||||
device lapic 1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -56,12 +56,12 @@ chip northbridge/amd/amdk8/root_complex
|
|||
device pci 19.3 on end
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/amd/socket_940
|
||||
device apic 1 on end
|
||||
device lapic 1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -54,9 +54,9 @@ chip northbridge/via/cn700 # Northbridge
|
|||
device pci 12.0 on end # Ethernet
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/via/model_c7 # VIA C7
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -1,8 +1,8 @@
|
|||
chip northbridge/intel/i945
|
||||
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mFCPGA478
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
@ -9,9 +9,9 @@
|
|||
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
||||
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_S1G1
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -81,9 +81,9 @@ chip northbridge/amd/lx
|
|||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -82,9 +82,9 @@ chip northbridge/amd/lx
|
|||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -19,9 +19,9 @@
|
|||
##
|
||||
|
||||
chip northbridge/intel/i82810 # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_PGA370 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
|
|
|
@ -19,9 +19,9 @@
|
|||
##
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
|
|
|
@ -19,9 +19,9 @@
|
|||
##
|
||||
|
||||
chip northbridge/intel/i82810 # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_PGA370 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/amd/socket_754 # Socket 754 CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/amd/socket_AM2 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
@ -22,9 +22,9 @@
|
|||
##
|
||||
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_F_1207
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/intel/i82810 # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_PGA370 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,10 +1,10 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/amd/socket_940
|
||||
device apic 1 on end
|
||||
device lapic 1 on end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
@ -19,9 +19,9 @@
|
|||
##
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_PGA370 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
chip northbridge/amd/gx2
|
||||
register "irqmap" = "0xaa5b"
|
||||
register "setupflash" = "0"
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/model_gx2
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
chip northbridge/amd/gx2
|
||||
register "irqmap" = "0xaa5b"
|
||||
register "setupflash" = "0"
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/model_gx2
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -76,9 +76,9 @@ chip northbridge/amd/lx
|
|||
end
|
||||
|
||||
# APIC cluster is late CPU init.
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/intel/i82830 # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_mFCBGA479 # Mobile Celeron Micro-FCBGA Socket 479
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
|
|
|
@ -21,9 +21,9 @@
|
|||
|
||||
chip northbridge/intel/i945
|
||||
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mFCPGA478
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
@ -19,9 +19,9 @@
|
|||
##
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdfam10/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_F_1207
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdfam10/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_F_1207
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -52,12 +52,12 @@ chip northbridge/intel/e7525 # mch
|
|||
device pci 04.0 on end
|
||||
device pci 08.0 on end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu0
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # cpu1
|
||||
device apic 6 on end
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -75,12 +75,12 @@ chip northbridge/intel/e7520 # MCH
|
|||
device pci 06.0 on end
|
||||
end
|
||||
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # CPU 0
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # CPU 1
|
||||
device apic 6 on end
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -75,12 +75,12 @@ chip northbridge/intel/e7520 # MCH
|
|||
device pci 06.0 on end
|
||||
end
|
||||
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # CPU 0
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # CPU 1
|
||||
device apic 6 on end
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -71,12 +71,12 @@ chip northbridge/intel/e7520 # mch
|
|||
end
|
||||
device pci 06.0 on end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu 0
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # cpu 1
|
||||
device apic 6 on end
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
register "intrline" = "0x00070105"
|
||||
|
|
|
@ -62,12 +62,12 @@ chip northbridge/intel/e7520 # mch
|
|||
device pci 04.0 on end
|
||||
device pci 06.0 on end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu 0
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # cpu 1
|
||||
device apic 6 on end
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
register "intrline" = "0x00070105"
|
||||
|
|
|
@ -9,9 +9,9 @@
|
|||
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
||||
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_S1G1
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -9,9 +9,9 @@
|
|||
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
||||
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_S1G1
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/intel/i82830 # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_mFCBGA479 # Low Voltage PIII Micro-FCBGA Socket 479
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device apic 0 on end # APIC
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
|
|
|
@ -73,12 +73,12 @@ chip northbridge/intel/e7501
|
|||
device pci 1f.6 off end
|
||||
end # SB
|
||||
end # PCI_DOMAIN
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604
|
||||
device apic 6 on end
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue