mb/google/slippy: Factor out common romstage settings
There's no need to repeat the same values over four variants. Change-Id: Ifc4a9961fe9c87f15a6039e6e478682fab5b0bb7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
parent
e12de372d7
commit
8d3bc49876
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@ -1,10 +1,89 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/romstage.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/raminit.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include "variant.h"
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const struct rcba_config_instruction rcba_config[] = {
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/*
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* GFX INTA -> PIRQA (MSI)
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* D28IP_P1IP PCIE INTA -> PIRQA
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* D29IP_E1P EHCI INTA -> PIRQD
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* D20IP_XHCI XHCI INTA -> PIRQC (MSI)
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* D31IP_SIP SATA INTA -> PIRQF (MSI)
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* D31IP_SMIP SMBUS INTB -> PIRQG
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* D31IP_TTIP THRT INTC -> PIRQA
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* D27IP_ZIP HDA INTA -> PIRQG (MSI)
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*/
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/* Device interrupt pin register (board specific) */
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RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
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(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
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RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
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RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
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(INTB << D28IP_P4IP)),
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RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
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RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
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RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
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RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
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/* Device interrupt route registers */
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RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
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RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
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RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
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RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
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RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
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RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
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RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
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RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
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/* Disable unused devices (board specific) */
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RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
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RCBA_END_CONFIG,
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};
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void mainboard_romstage_entry(void)
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{
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variant_romstage_entry();
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struct pei_data pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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.epbar = DEFAULT_EPBAR,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = SMBUS_IO_BASE,
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.hpet_address = HPET_ADDR,
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.rcba = (uintptr_t)DEFAULT_RCBA,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.temp_mmio_base = 0xfed08000,
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.system_type = 5, /* ULT */
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
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.ec_present = 1,
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/*
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* 0 = leave channel enabled
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* 1 = disable dimm 0 on channel
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* 2 = disable dimm 1 on channel
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* 3 = disable dimm 0+1 on channel
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*/
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.dimm_channel0_disabled = 2,
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.dimm_channel1_disabled = 2,
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.max_ddr3_freq = 1600,
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.usb_xhci_on_resume = 1,
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};
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.rcba_config = rcba_config,
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};
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variant_romstage_entry(&romstage_params);
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/* Call into the real romstage main with this board's attributes. */
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romstage_common(&romstage_params);
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}
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@ -3,6 +3,6 @@
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#ifndef VARIANT_H
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#define VARIANT_H
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void variant_romstage_entry(void);
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void variant_romstage_entry(struct romstage_params *rp);
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#endif
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@ -13,46 +13,6 @@
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#include <variant/gpio.h>
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#include "../../variant.h"
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const struct rcba_config_instruction rcba_config[] = {
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/*
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* GFX INTA -> PIRQA (MSI)
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* D28IP_P1IP PCIE INTA -> PIRQA
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* D29IP_E1P EHCI INTA -> PIRQD
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* D20IP_XHCI XHCI INTA -> PIRQC (MSI)
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* D31IP_SIP SATA INTA -> PIRQF (MSI)
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* D31IP_SMIP SMBUS INTB -> PIRQG
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* D31IP_TTIP THRT INTC -> PIRQA
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* D27IP_ZIP HDA INTA -> PIRQG (MSI)
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*/
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/* Device interrupt pin register (board specific) */
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RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
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(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
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RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
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RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
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(INTB << D28IP_P4IP)),
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RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
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RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
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RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
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RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
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/* Device interrupt route registers */
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RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
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RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
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RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
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RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
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RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
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RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
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RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
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RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
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/* Disable unused devices (board specific) */
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RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
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RCBA_END_CONFIG,
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};
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/* Copy SPD data for on-board memory */
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static void copy_spd(struct pei_data *peid)
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{
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}
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}
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void variant_romstage_entry(void)
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void variant_romstage_entry(struct romstage_params *rp)
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{
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struct pei_data pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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.epbar = DEFAULT_EPBAR,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = SMBUS_IO_BASE,
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.hpet_address = HPET_ADDR,
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.rcba = (uintptr_t)DEFAULT_RCBA,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.temp_mmio_base = 0xfed08000,
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.system_type = 5, /* ULT */
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
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.ec_present = 1,
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// 0 = leave channel enabled
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// 1 = disable dimm 0 on channel
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// 2 = disable dimm 1 on channel
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// 3 = disable dimm 0+1 on channel
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.dimm_channel0_disabled = 2,
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.dimm_channel1_disabled = 2,
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// Enable 2x refresh mode
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.ddr_refresh_2x = 1,
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.max_ddr3_freq = 1600,
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.usb_xhci_on_resume = 1,
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.usb2_ports = {
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/* Length, Enable, OCn#, Location */
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{ 0x0064, 1, 0, /* P0: Port A, CN8 */
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USB_PORT_BACK_PANEL },
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{ 0x0052, 1, 0, /* P1: Port B, CN9 */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
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USB_PORT_INTERNAL },
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{ 0x0123, 1, 3, /* P7: USB2 Port */
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USB_PORT_INTERNAL },
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},
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.usb3_ports = {
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/* Enable, OCn# */
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{ 1, 0 }, /* P1; Port A, CN8 */
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{ 1, 0 }, /* P2; Port B, CN9 */
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{ 0, USB_OC_PIN_SKIP }, /* P3; */
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{ 0, USB_OC_PIN_SKIP }, /* P4; */
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},
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rp->pei_data->ddr_refresh_2x = 1; /* Enable 2x refresh mode */
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
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/* Length, Enable, OCn#, Location */
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{ 0x0064, 1, 0, /* P0: Port A, CN8 */
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USB_PORT_BACK_PANEL },
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{ 0x0052, 1, 0, /* P1: Port B, CN9 */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
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USB_PORT_INTERNAL },
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{ 0x0123, 1, 3, /* P7: USB2 Port */
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USB_PORT_INTERNAL },
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};
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.gpio_map = &mainboard_gpio_map,
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.rcba_config = &rcba_config[0],
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.copy_spd = copy_spd,
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struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
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/* Enable, OCn# */
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{ 1, 0 }, /* P1; Port A, CN8 */
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{ 1, 0 }, /* P2; Port B, CN9 */
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{ 0, USB_OC_PIN_SKIP }, /* P3; */
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{ 0, USB_OC_PIN_SKIP }, /* P4; */
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};
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/* Call into the real romstage main with this board's attributes. */
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romstage_common(&romstage_params);
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memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
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memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
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rp->gpio_map = &mainboard_gpio_map;
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rp->copy_spd = copy_spd;
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}
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@ -12,46 +12,6 @@
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#include <variant/gpio.h>
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#include "../../variant.h"
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const struct rcba_config_instruction rcba_config[] = {
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/*
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* GFX INTA -> PIRQA (MSI)
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* D28IP_P1IP PCIE INTA -> PIRQA
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* D29IP_E1P EHCI INTA -> PIRQD
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* D20IP_XHCI XHCI INTA -> PIRQC (MSI)
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* D31IP_SIP SATA INTA -> PIRQF (MSI)
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* D31IP_SMIP SMBUS INTB -> PIRQG
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* D31IP_TTIP THRT INTC -> PIRQA
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* D27IP_ZIP HDA INTA -> PIRQG (MSI)
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*/
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/* Device interrupt pin register (board specific) */
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RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
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(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
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RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
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RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
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(INTB << D28IP_P4IP)),
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RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
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RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
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RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
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RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
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/* Device interrupt route registers */
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RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
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RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
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RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
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RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
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RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
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RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
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RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
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RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
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/* Disable unused devices (board specific) */
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RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
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RCBA_END_CONFIG,
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};
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/* Copy SPD data for on-board memory */
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static void copy_spd(struct pei_data *peid)
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{
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spd_file + (spd_index * spd_len), spd_len);
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}
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void variant_romstage_entry(void)
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void variant_romstage_entry(struct romstage_params *rp)
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{
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struct pei_data pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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.epbar = DEFAULT_EPBAR,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = SMBUS_IO_BASE,
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.hpet_address = HPET_ADDR,
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.rcba = (uintptr_t)DEFAULT_RCBA,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.temp_mmio_base = 0xfed08000,
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.system_type = 5, /* ULT */
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
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.ec_present = 1,
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// 0 = leave channel enabled
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// 1 = disable dimm 0 on channel
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// 2 = disable dimm 1 on channel
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// 3 = disable dimm 0+1 on channel
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.dimm_channel0_disabled = 2,
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.dimm_channel1_disabled = 2,
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.max_ddr3_freq = 1600,
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.usb_xhci_on_resume = 1,
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.usb2_ports = {
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/* Length, Enable, OCn#, Location */
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{ 0x0040, 1, 0, /* P0: Port A, CN10 */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, 2, /* P1: Port B, CN11 */
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USB_PORT_BACK_PANEL },
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{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
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USB_PORT_MINI_PCIE },
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{ 0x0080, 1, USB_OC_PIN_SKIP, /* P4: SD Card */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: LTE */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SIM CARD */
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USB_PORT_FLEX },
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{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
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USB_PORT_SKIP },
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},
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.usb3_ports = {
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/* Enable, OCn# */
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{ 1, 0 }, /* P1; Port A, CN10 */
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{ 1, 2 }, /* P2; Port B, CN11 */
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{ 0, USB_OC_PIN_SKIP }, /* P3; */
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{ 0, USB_OC_PIN_SKIP }, /* P4; */
|
||||
},
|
||||
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
|
||||
/* Length, Enable, OCn#, Location */
|
||||
{ 0x0040, 1, 0, /* P0: Port A, CN10 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 2, /* P1: Port B, CN11 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
|
||||
USB_PORT_MINI_PCIE },
|
||||
{ 0x0080, 1, USB_OC_PIN_SKIP, /* P4: SD Card */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: LTE */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SIM CARD */
|
||||
USB_PORT_FLEX },
|
||||
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
|
||||
USB_PORT_SKIP },
|
||||
};
|
||||
|
||||
struct romstage_params romstage_params = {
|
||||
.pei_data = &pei_data,
|
||||
.gpio_map = &mainboard_gpio_map,
|
||||
.rcba_config = &rcba_config[0],
|
||||
.copy_spd = copy_spd,
|
||||
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
|
||||
/* Enable, OCn# */
|
||||
{ 1, 0 }, /* P1; Port A, CN10 */
|
||||
{ 1, 2 }, /* P2; Port B, CN11 */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P3; */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P4; */
|
||||
};
|
||||
|
||||
/* Call into the real romstage main with this board's attributes. */
|
||||
romstage_common(&romstage_params);
|
||||
memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
|
||||
memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
|
||||
|
||||
rp->gpio_map = &mainboard_gpio_map;
|
||||
rp->copy_spd = copy_spd;
|
||||
}
|
||||
|
|
|
@ -14,46 +14,6 @@
|
|||
#include "../../onboard.h"
|
||||
#include "../../variant.h"
|
||||
|
||||
const struct rcba_config_instruction rcba_config[] = {
|
||||
|
||||
/*
|
||||
* GFX INTA -> PIRQA (MSI)
|
||||
* D28IP_P1IP PCIE INTA -> PIRQA
|
||||
* D29IP_E1P EHCI INTA -> PIRQD
|
||||
* D20IP_XHCI XHCI INTA -> PIRQC (MSI)
|
||||
* D31IP_SIP SATA INTA -> PIRQF (MSI)
|
||||
* D31IP_SMIP SMBUS INTB -> PIRQG
|
||||
* D31IP_TTIP THRT INTC -> PIRQA
|
||||
* D27IP_ZIP HDA INTA -> PIRQG (MSI)
|
||||
*/
|
||||
|
||||
/* Device interrupt pin register (board specific) */
|
||||
RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
|
||||
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
|
||||
RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
|
||||
RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
|
||||
(INTB << D28IP_P4IP)),
|
||||
RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
|
||||
RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
|
||||
RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
|
||||
RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
|
||||
|
||||
/* Device interrupt route registers */
|
||||
RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
|
||||
RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
|
||||
RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
|
||||
RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
|
||||
RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
|
||||
RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
|
||||
RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
|
||||
RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
|
||||
|
||||
/* Disable unused devices (board specific) */
|
||||
RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
|
||||
|
||||
RCBA_END_CONFIG,
|
||||
};
|
||||
|
||||
/* Copy SPD data for on-board memory */
|
||||
static void copy_spd(struct pei_data *peid)
|
||||
{
|
||||
|
@ -104,67 +64,39 @@ static void copy_spd(struct pei_data *peid)
|
|||
}
|
||||
}
|
||||
|
||||
void variant_romstage_entry(void)
|
||||
void variant_romstage_entry(struct romstage_params *rp)
|
||||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
.system_type = 5, /* ULT */
|
||||
.tseg_size = CONFIG_SMM_TSEG_SIZE,
|
||||
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
|
||||
.ec_present = 1,
|
||||
// 0 = leave channel enabled
|
||||
// 1 = disable dimm 0 on channel
|
||||
// 2 = disable dimm 1 on channel
|
||||
// 3 = disable dimm 0+1 on channel
|
||||
.dimm_channel0_disabled = 2,
|
||||
.dimm_channel1_disabled = 2,
|
||||
.max_ddr3_freq = 1600,
|
||||
.usb_xhci_on_resume = 1,
|
||||
.usb2_ports = {
|
||||
/* Length, Enable, OCn#, Location */
|
||||
{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
|
||||
USB_PORT_MINI_PCIE },
|
||||
{ 0x0040, 1, 0, /* P1: Port A, CN10 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
|
||||
USB_PORT_MINI_PCIE },
|
||||
{ 0x0040, 1, 2, /* P4: Port B, CN6 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
|
||||
USB_PORT_SKIP },
|
||||
{ 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
|
||||
USB_PORT_FLEX },
|
||||
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
|
||||
USB_PORT_SKIP },
|
||||
},
|
||||
.usb3_ports = {
|
||||
/* Enable, OCn# */
|
||||
{ 1, 0 }, /* P1; Port A, CN6 */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P2; */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P3; */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P4; */
|
||||
},
|
||||
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
|
||||
/* Length, Enable, OCn#, Location */
|
||||
{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
|
||||
USB_PORT_MINI_PCIE },
|
||||
{ 0x0040, 1, 0, /* P1: Port A, CN10 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
|
||||
USB_PORT_MINI_PCIE },
|
||||
{ 0x0040, 1, 2, /* P4: Port B, CN6 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
|
||||
USB_PORT_SKIP },
|
||||
{ 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
|
||||
USB_PORT_FLEX },
|
||||
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
|
||||
USB_PORT_SKIP },
|
||||
};
|
||||
|
||||
struct romstage_params romstage_params = {
|
||||
.pei_data = &pei_data,
|
||||
.gpio_map = &mainboard_gpio_map,
|
||||
.rcba_config = &rcba_config[0],
|
||||
.copy_spd = copy_spd,
|
||||
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
|
||||
/* Enable, OCn# */
|
||||
{ 1, 0 }, /* P1; Port A, CN6 */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P2; */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P3; */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P4; */
|
||||
};
|
||||
|
||||
/* Call into the real romstage main with this board's attributes. */
|
||||
romstage_common(&romstage_params);
|
||||
memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
|
||||
memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
|
||||
|
||||
rp->gpio_map = &mainboard_gpio_map;
|
||||
rp->copy_spd = copy_spd;
|
||||
}
|
||||
|
|
|
@ -13,46 +13,6 @@
|
|||
#include <variant/gpio.h>
|
||||
#include "../../variant.h"
|
||||
|
||||
const struct rcba_config_instruction rcba_config[] = {
|
||||
|
||||
/*
|
||||
* GFX INTA -> PIRQA (MSI)
|
||||
* D28IP_P1IP PCIE INTA -> PIRQA
|
||||
* D29IP_E1P EHCI INTA -> PIRQD
|
||||
* D20IP_XHCI XHCI INTA -> PIRQC (MSI)
|
||||
* D31IP_SIP SATA INTA -> PIRQF (MSI)
|
||||
* D31IP_SMIP SMBUS INTB -> PIRQG
|
||||
* D31IP_TTIP THRT INTC -> PIRQA
|
||||
* D27IP_ZIP HDA INTA -> PIRQG (MSI)
|
||||
*/
|
||||
|
||||
/* Device interrupt pin register (board specific) */
|
||||
RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
|
||||
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
|
||||
RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
|
||||
RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
|
||||
(INTB << D28IP_P4IP)),
|
||||
RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
|
||||
RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
|
||||
RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
|
||||
RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
|
||||
|
||||
/* Device interrupt route registers */
|
||||
RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
|
||||
RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
|
||||
RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
|
||||
RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
|
||||
RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
|
||||
RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
|
||||
RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
|
||||
RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
|
||||
|
||||
/* Disable unused devices (board specific) */
|
||||
RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
|
||||
|
||||
RCBA_END_CONFIG,
|
||||
};
|
||||
|
||||
/* Copy SPD data for on-board memory */
|
||||
static void copy_spd(struct pei_data *peid)
|
||||
{
|
||||
|
@ -91,67 +51,39 @@ static void copy_spd(struct pei_data *peid)
|
|||
}
|
||||
}
|
||||
|
||||
void variant_romstage_entry(void)
|
||||
void variant_romstage_entry(struct romstage_params *rp)
|
||||
{
|
||||
struct pei_data pei_data = {
|
||||
.pei_version = PEI_VERSION,
|
||||
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||
.epbar = DEFAULT_EPBAR,
|
||||
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
|
||||
.smbusbar = SMBUS_IO_BASE,
|
||||
.hpet_address = HPET_ADDR,
|
||||
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||
.pmbase = DEFAULT_PMBASE,
|
||||
.gpiobase = DEFAULT_GPIOBASE,
|
||||
.temp_mmio_base = 0xfed08000,
|
||||
.system_type = 5, /* ULT */
|
||||
.tseg_size = CONFIG_SMM_TSEG_SIZE,
|
||||
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
|
||||
.ec_present = 1,
|
||||
// 0 = leave channel enabled
|
||||
// 1 = disable dimm 0 on channel
|
||||
// 2 = disable dimm 1 on channel
|
||||
// 3 = disable dimm 0+1 on channel
|
||||
.dimm_channel0_disabled = 2,
|
||||
.dimm_channel1_disabled = 2,
|
||||
.max_ddr3_freq = 1600,
|
||||
.usb_xhci_on_resume = 1,
|
||||
.usb2_ports = {
|
||||
/* Length, Enable, OCn#, Location */
|
||||
{ 0x0040, 1, 0, /* P0: Port A, CN10 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 2, /* P1: Port B, CN11 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
|
||||
USB_PORT_MINI_PCIE },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */
|
||||
USB_PORT_SKIP },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
|
||||
USB_PORT_SKIP },
|
||||
},
|
||||
.usb3_ports = {
|
||||
/* Enable, OCn# */
|
||||
{ 1, 0 }, /* P1; Port A, CN10 */
|
||||
{ 1, 2 }, /* P2; Port B, CN11 */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P3; */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P4; */
|
||||
},
|
||||
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
|
||||
/* Length, Enable, OCn#, Location */
|
||||
{ 0x0040, 1, 0, /* P0: Port A, CN10 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0040, 1, 2, /* P1: Port B, CN11 */
|
||||
USB_PORT_BACK_PANEL },
|
||||
{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
|
||||
USB_PORT_MINI_PCIE },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */
|
||||
USB_PORT_SKIP },
|
||||
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
|
||||
USB_PORT_INTERNAL },
|
||||
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
|
||||
USB_PORT_SKIP },
|
||||
};
|
||||
|
||||
struct romstage_params romstage_params = {
|
||||
.pei_data = &pei_data,
|
||||
.gpio_map = &mainboard_gpio_map,
|
||||
.rcba_config = &rcba_config[0],
|
||||
.copy_spd = copy_spd,
|
||||
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
|
||||
/* Enable, OCn# */
|
||||
{ 1, 0 }, /* P1; Port A, CN10 */
|
||||
{ 1, 2 }, /* P2; Port B, CN11 */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P3; */
|
||||
{ 0, USB_OC_PIN_SKIP }, /* P4; */
|
||||
};
|
||||
|
||||
/* Call into the real romstage main with this board's attributes. */
|
||||
romstage_common(&romstage_params);
|
||||
memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
|
||||
memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
|
||||
|
||||
rp->gpio_map = &mainboard_gpio_map;
|
||||
rp->copy_spd = copy_spd;
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue