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soc/intel/tigerlake: Add known GPIO virtual wire information 

GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at
least some of their groups; add the known information into the community
definitions.

Change-Id: Icc4581e61ee904cbd998738962d360a58d24bc35
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-05-03 13:05:12 -06:00
parent 629ddfd265
commit 8d3cc1bcc2
1 changed files with 27 additions and 0 deletions
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27
src/soc/intel/tigerlake/gpio.c
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@ -5,6 +5,8 @@
#include <soc/pcr_ids.h>
#include <soc/pmc.h>
#define DEFAULT_VW_BASE 0x10
/*
* This file is created based on Intel Tiger Lake Processor PCH Datasheet
* Document number: 575857
@ -42,6 +44,11 @@ static const struct pad_group tgl_community0_groups[] = {
INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64), /* GPP_A */
};
static const struct vw_entries tgl_community0_vw[] = {
{GPP_A0, GPP_A23},
{GPP_B0, GPP_B23},
};
static const struct pad_group tgl_community1_groups[] = {
INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */
INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */
@ -50,6 +57,11 @@ static const struct pad_group tgl_community1_groups[] = {
INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224), /* GPP_VGPIO */
};
static const struct vw_entries tgl_community1_vw[] = {
{GPP_D0, GPP_D19},
{GPP_H0, GPP_H23},
};
/* This community is not visible to the OS */
static const struct pad_group tgl_community2_groups[] = {
INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */
@ -63,6 +75,12 @@ static const struct pad_group tgl_community4_groups[] = {
INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */
};
static const struct vw_entries tgl_community4_vw[] = {
{GPP_F0, GPP_F23},
{GPP_C0, GPP_C23},
{GPP_E0, GPP_E23},
};
static const struct pad_group tgl_community5_groups[] = {
INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */
INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */
@ -87,6 +105,9 @@ static const struct pad_community tgl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = tgl_community0_groups,
.num_groups = ARRAY_SIZE(tgl_community0_groups),
.vw_base = DEFAULT_VW_BASE,
.vw_entries = tgl_community0_vw,
.num_vw_entries = ARRAY_SIZE(tgl_community0_vw),
},
[COMM_1] = { /* GPP S, D, H, U, VGPIO */
.port = PID_GPIOCOM1,
@ -106,6 +127,9 @@ static const struct pad_community tgl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = tgl_community1_groups,
.num_groups = ARRAY_SIZE(tgl_community1_groups),
.vw_base = DEFAULT_VW_BASE,
.vw_entries = tgl_community1_vw,
.num_vw_entries = ARRAY_SIZE(tgl_community1_vw),
},
[COMM_2] = { /* GPD */
.port = PID_GPIOCOM2,
@ -144,6 +168,9 @@ static const struct pad_community tgl_communities[] = {
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = tgl_community4_groups,
.num_groups = ARRAY_SIZE(tgl_community4_groups),
.vw_base = DEFAULT_VW_BASE,
.vw_entries = tgl_community4_vw,
.num_vw_entries = ARRAY_SIZE(tgl_community4_vw),
},
[COMM_5] = { /* GPP R, SPI */
.port = PID_GPIOCOM5,