GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/{jsl,tgl}: Refactor gpio_op.asl 

Also align GPMO ASL function with TGL.

Change-Id: Ia40af2cba9867838a1f99141481a5e78cffa0111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2020-09-24 18:23:23 +05:30
parent 63ee16075e
commit 8d4176109d
2 changed files with 14 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/soc/intel/jasperlake/acpi/gpio_op.asl
View File

@ -43,7 +43,7 @@ Method (STXS, 1, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
VAL0 = PAD_CFG0_TX_STATE | VAL0 VAL0 |= PAD_CFG0_TX_STATE
} }
/* /*
@ -57,7 +57,7 @@ Method (CTXS, 1, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
VAL0 = ~PAD_CFG0_TX_STATE & VAL0 VAL0 &= ~PAD_CFG0_TX_STATE
} }
/* /*
@ -76,9 +76,8 @@ Method (GPMO, 2, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
Local0 = VAL0 Local0 = ~PAD_CFG0_MODE_MASK & VAL0
Local0 = ~PAD_CFG0_MODE_MASK & Local0 Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK
Arg1 = (Arg1 <<= PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK
VAL0 = Local0 | Arg1 VAL0 = Local0 | Arg1
} }
@ -98,9 +97,9 @@ Method (GTXE, 2, Serialized)
} }
If (Arg1 == 1) { If (Arg1 == 1) {
VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0 VAL0 &= ~PAD_CFG0_TX_DISABLE
} ElseIf (Arg1 == 0){ } ElseIf (Arg1 == 0){
VAL0 = PAD_CFG0_TX_DISABLE | VAL0 VAL0 &= PAD_CFG0_TX_DISABLE
} }
} }
@ -120,8 +119,8 @@ Method (GRXE, 2, Serialized)
} }
If (Arg1 == 1) { If (Arg1 == 1) {
VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0 VAL0 &= ~PAD_CFG0_RX_DISABLE
} ElseIf (Arg1 == 0){ } ElseIf (Arg1 == 0){
VAL0 = PAD_CFG0_RX_DISABLE | VAL0 VAL0 |= PAD_CFG0_RX_DISABLE
} }
} }

12
src/soc/intel/tigerlake/acpi/gpio_op.asl
View File

@ -43,7 +43,7 @@ Method (STXS, 1, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
VAL0 = PAD_CFG0_TX_STATE | VAL0 VAL0 |= PAD_CFG0_TX_STATE
} }
/* /*
@ -57,7 +57,7 @@ Method (CTXS, 1, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
VAL0 = ~PAD_CFG0_TX_STATE & VAL0 VAL0 &= ~PAD_CFG0_TX_STATE
} }
/* /*
@ -97,9 +97,9 @@ Method (GTXE, 2, Serialized)
} }
If (Arg1 == 1) { If (Arg1 == 1) {
VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0 VAL0 &= ~PAD_CFG0_TX_DISABLE
} ElseIf (Arg1 == 0){ } ElseIf (Arg1 == 0){
VAL0 = PAD_CFG0_TX_DISABLE | VAL0 VAL0 &= PAD_CFG0_TX_DISABLE
} }
} }
@ -119,8 +119,8 @@ Method (GRXE, 2, Serialized)
} }
If (Arg1 == 1) { If (Arg1 == 1) {
VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0 VAL0 &= ~PAD_CFG0_RX_DISABLE
} ElseIf (Arg1 == 0){ } ElseIf (Arg1 == 0){
VAL0 = PAD_CFG0_RX_DISABLE | VAL0 VAL0 |= PAD_CFG0_RX_DISABLE
} }
} }