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in loglevel.h, if ASM_CONSOLE_LOGLEVEL is defined, don't try to set it. 

Set adl855pc ROM_SIZE to 1M
Other minor debug prints until we get this fixed.

We're almost as far along as we were before the Change :-)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2004-11-11 14:04:25 +00:00
parent 029517c77a
commit 8d41ad83be
5 changed files with 26 additions and 5 deletions
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2
src/include/console/loglevel.h
View File

@ -11,11 +11,13 @@
#define DEFAULT_CONSOLE_LOGLEVEL 8 /* anything MORE serious than BIOS_SPEW */
#endif
#ifndef ASM_CONSOLE_LOGLEVEL
#if (DEFAULT_CONSOLE_LOGLEVEL <= MAXIMUM_CONSOLE_LOGLEVEL)
#define ASM_CONSOLE_LOGLEVEL DEFAULT_CONSOLE_LOGLEVEL
#else
#define ASM_CONSOLE_LOGLEVEL MAXIMUM_CONSOLE_LOGLEVEL
#endif
#endif
#define BIOS_EMERG 0 /* system is unusable */
#define BIOS_ALERT 1 /* action must be taken immediately */

6
src/mainboard/digitallogic/adl855pc/Options.lb
View File

@ -32,8 +32,12 @@ uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
default DEFAULT_CONSOLE_LOGLEVEL=9
default MAXIMUM_CONSOLE_LOGLEVEL=9
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
default ROM_SIZE = 1024*1024
###
### Build options

11
src/mainboard/digitallogic/adl855pc/auto.c
View File

@ -1,5 +1,5 @@
#define ASSEMBLY 1
#define ASM_CONSOLE_LOGLEVEL 10
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
@ -80,22 +80,29 @@ static void main(unsigned long bist)
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
print_err("HARD MAIN0\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
#if 0
print_err("HARD MAIN\n");
#if 1
print_pci_devices();
#endif
print_err("after print pci dev \n");
if(!bios_reset_detected()) {
enable_smbus();
print_err("after enable smbus\n");
#if 1
dump_spd_registers(&memctrl[0]);
// dump_smbus_registers();
#endif
print_err("after dump spd registers\n");
memreset_setup();
print_err("memreset setup\n");
sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
print_err("sdram init\n");
}
#if 0
else {

4
src/northbridge/intel/i855pm/raminit.c
View File

@ -17,9 +17,9 @@
/* converted to C 6/2004 yhlu */
#define DEBUG_RAM_CONFIG 1
#define DEBUG_RAM_CONFIG 12
#undef ASM_CONSOLE_LOGLEVEL
#define ASM_CONSOLE_LOGLEVEL 9
#define ASM_CONSOLE_LOGLEVEL 10
#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1))
/* DDR DIMM Mode register Definitions */

8
src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
View File

@ -105,7 +105,9 @@ static int smbus_read_byte(unsigned device, unsigned address)
unsigned char global_status_register;
unsigned char byte;
print_err("smbus_read_byte\r\n");
if (smbus_wait_until_ready() < 0) {
print_err_hex8(-2);
return -2;
}
@ -129,11 +131,13 @@ static int smbus_read_byte(unsigned device, unsigned address)
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
/* poll for it to start */
if (smbus_wait_until_active() < 0) {
print_err_hex8(-4);
return -4;
}
/* poll for transaction completion */
if (smbus_wait_until_done() < 0) {
print_err_hex8(-3);
return -3;
}
@ -143,8 +147,12 @@ static int smbus_read_byte(unsigned device, unsigned address)
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
if (global_status_register != 2) {
print_err_hex8(-1);
return -1;
}
print_err("smbus_read_byte: ");
print_err_hex32(device); print_err(" ad "); print_err_hex32(address);
print_err("value "); print_err_hex8(byte); print_err("\r\n");
return byte;
}
#if 0