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cbfstool: clarify dependencies in Makefile 

While logical, make's handling of multiple targets in a rule isn't
intuitive, and was done wrong in cbfstool's Makefile.

%.c %.h: %.l encourages make to run the rule twice, once to
generate the .c file, once for the .h file. Hilarity ensues.

Change-Id: I2560cb34b6aee5f4bdd764bb05bb69ea2789c7d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10251
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2015-05-19 16:41:21 +02:00 committed by Patrick Georgi
parent d32b27383b
commit 8d6e24c739
1 changed files with 6 additions and 2 deletions
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8
util/cbfstool/Makefile
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@ -54,9 +54,13 @@ $(obj)/%: $(obj)/%.o
$(obj)/%.o: %.c $(obj)/%.o: %.c
mkdir -p $(dir $@) mkdir -p $(dir $@)
$(HOSTCC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $< $(HOSTCC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<
%.c %.h: %.l
fmd_scanner.h: fmd_scanner.c
fmd_scanner.c: fmd_scanner.l
$(LEX) $(LFLAGS) -t --header-file=$*.h $< >$*.c $(LEX) $(LFLAGS) -t --header-file=$*.h $< >$*.c
%.c %.h: %.y
fmd_parser.h: fmd_parser.c
fmd_parser.c: fmd_parser.y
$(YACC) $(YFLAGS) -d $< $(YACC) $(YFLAGS) -d $<
mv -f y.tab.c $*.c mv -f y.tab.c $*.c
mv -f y.tab.h $*.h mv -f y.tab.h $*.h