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mb/tglrvp: update gpio pin mux for NVMe 

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from NVMe

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38286
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-01-08 14:25:55 -08:00 committed by Subrata Banik
parent 5abeb06a73
commit 8d6eae5d6d
1 changed files with 3 additions and 1 deletions
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4
src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
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@ -19,7 +19,9 @@
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
/* ToDo: Fill gpio configuration */
/* PCH M.2 SSD */
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
};
/* Early pad configuration in bootblock */