soc/intel/common/block/p2sb/p2sb: Add missing PCI IDs
The code is compiled on SKL/KBL, but the P2SB PCI IDs were missing. Add them to make sure that the BAR0 doesn't change when running PCI resource allocation. Change-Id: I7cffbbc7d15dad14cccd122a081099b51dc1ce07 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -3265,6 +3265,9 @@
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#define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192
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#define PCI_DEVICE_ID_INTEL_LWB_P2SB 0xa1a0
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#define PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER 0xa220
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#define PCI_DEVICE_ID_INTEL_SKL_LP_P2SB 0x9d20
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#define PCI_DEVICE_ID_INTEL_SKL_P2SB 0xa120
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#define PCI_DEVICE_ID_INTEL_KBL_P2SB 0xa2a0
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#define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0
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#define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320
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#define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0
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@ -155,6 +155,8 @@ static void read_resources(struct device *dev)
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/*
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* There's only one resource on the P2SB device. It's also already
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* manually set to a fixed address in earlier boot stages.
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* The following code makes sure that it doesn't change if the device
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* is visible and the resource allocator is being run.
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*/
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mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB);
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}
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@ -170,6 +172,9 @@ static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_GLK_P2SB,
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PCI_DEVICE_ID_INTEL_LWB_P2SB,
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PCI_DEVICE_ID_INTEL_LWB_P2SB_SUPER,
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PCI_DEVICE_ID_INTEL_SKL_LP_P2SB,
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PCI_DEVICE_ID_INTEL_SKL_P2SB,
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PCI_DEVICE_ID_INTEL_KBL_P2SB,
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PCI_DEVICE_ID_INTEL_CNL_P2SB,
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PCI_DEVICE_ID_INTEL_CNP_H_P2SB,
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PCI_DEVICE_ID_INTEL_ICL_P2SB,
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