ASRock DSDT: Split the ASRock DSDT
This is the same split as was done on the Persimmon. Change-Id: I25bd63f23417b7926232f07eaaa7917170af9d60 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3050 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Mike Loptien
Ronald G. Minnich
parent
b48605da20
commit
8d80a3fb9f
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@ -0,0 +1,84 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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Scope(\_GPE) { /* Start Scope GPE */
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/* General event 3 */
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Method(_L03) {
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/* DBGO("\\_GPE\\_L00\n") */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* Legacy PM event */
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Method(_L08) {
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/* DBGO("\\_GPE\\_L08\n") */
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}
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/* Temp warning (TWarn) event */
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Method(_L09) {
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/* DBGO("\\_GPE\\_L09\n") */
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/* Notify (\_TZ.TZ00, 0x80) */
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}
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/* USB controller PME# */
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Method(_L0B) {
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/* DBGO("\\_GPE\\_L0B\n") */
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Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* ExtEvent0 SCI event */
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Method(_L10) {
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/* DBGO("\\_GPE\\_L10\n") */
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}
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/* ExtEvent1 SCI event */
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Method(_L11) {
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/* DBGO("\\_GPE\\_L11\n") */
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}
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/* GPIO0 or GEvent8 event */
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Method(_L18) {
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/* DBGO("\\_GPE\\_L18\n") */
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Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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/* Azalia SCI event */
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Method(_L1B) {
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/* DBGO("\\_GPE\\_L1B\n") */
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Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
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Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
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}
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} /* End Scope GPE */
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/* Contains the GPEs for USB overcurrent */
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#include "usb_oc.asl"
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@ -0,0 +1,67 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Data to be patched by the BIOS during POST */
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/* FIXME the patching is not done yet! */
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/* Memory related values */
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Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
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Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
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Name(PBLN, 0x0) /* Length of BIOS area */
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Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
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Name(HPBA, 0xFED00000) /* Base address of HPET table */
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Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
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/* Some global data */
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Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
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Name(OSV, Ones) /* Assume nothing */
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Name(PMOD, One) /* Assume APIC */
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Scope(\_SB) {
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Method(CkOT, 0){
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if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
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if(CondRefOf(\_OSI,Local1))
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{
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Store(1, OSTP) /* Assume some form of XP */
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if (\_OSI("Windows 2006")) /* Vista */
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{
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Store(2, OSTP)
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}
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} else {
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If(WCMP(\_OS,"Linux")) {
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Store(3, OSTP) /* Linux */
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} Else {
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Store(4, OSTP) /* Gotta be WinCE */
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}
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}
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Return(OSTP)
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}
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}
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Scope(\_SI) {
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Method(_SST, 1) {
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/* DBGO("\\_SI\\_SST\n") */
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/* DBGO(" New Indicator state: ") */
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/* DBGO(Arg0) */
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/* DBGO("\n") */
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}
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} /* End Scope SI */
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@ -0,0 +1,121 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Wake status package */
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Name(WKST,Package(){Zero, Zero})
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/*
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* \_PTS - Prepare to Sleep method
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*
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* Entry:
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* Arg0=The value of the sleeping state S1=1, S2=2, etc
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*
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* Exit:
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* -none-
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*
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* The _PTS control method is executed at the beginning of the sleep process
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* for S1-S5. The sleeping value is passed to the _PTS control method. This
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* control method may be executed a relatively long time before entering the
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* sleep state and the OS may abort the operation without notification to
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* the ACPI driver. This method cannot modify the configuration or power
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* state of any device in the system.
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*/
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Method(\_PTS, 1) {
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/* DBGO("\\_PTS\n") */
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/* DBGO("From S0 to S") */
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/* DBGO(Arg0) */
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/* DBGO("\n") */
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/* Don't allow PCIRST# to reset USB */
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if (LEqual(Arg0,3)){
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Store(0,URRE)
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}
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/* Clear sleep SMI status flag and enable sleep SMI trap. */
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/*Store(One, CSSM)
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Store(One, SSEN)*/
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/* On older chips, clear PciExpWakeDisEn */
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/*if (LLessEqual(\_SB.SBRI, 0x13)) {
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* Store(0,\_SB.PWDE)
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*}
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*/
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/* Clear wake status structure. */
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Store(0, Index(WKST,0))
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Store(0, Index(WKST,1))
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} /* End Method(\_PTS) */
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/*
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* \_BFS OEM Back From Sleep method
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*
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* Entry:
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* Arg0=The value of the sleeping state S1=1, S2=2
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*
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* Exit:
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* -none-
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*/
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Method(\_BFS, 1) {
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/* DBGO("\\_BFS\n") */
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/* DBGO("From S") */
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/* DBGO(Arg0) */
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/* DBGO(" to S0\n") */
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}
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/*
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* \_WAK System Wake method
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*
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* Entry:
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* Arg0=The value of the sleeping state S1=1, S2=2
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*
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* Exit:
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* Return package of 2 DWords
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* Dword 1 - Status
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* 0x00000000 wake succeeded
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* 0x00000001 Wake was signaled but failed due to lack of power
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* 0x00000002 Wake was signaled but failed due to thermal condition
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* Dword 2 - Power Supply state
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* if non-zero the effective S-state the power supply entered
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*/
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Method(\_WAK, 1) {
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/* DBGO("\\_WAK\n") */
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/* DBGO("From S") */
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/* DBGO(Arg0) */
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/* DBGO(" to S0\n") */
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/* Re-enable HPET */
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Store(1,HPDE)
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/* Restore PCIRST# so it resets USB */
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if (LEqual(Arg0,3)){
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Store(1,URRE)
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}
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/* Arbitrarily clear PciExpWakeStatus */
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Store(PWST, PWST)
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/* if(DeRefOf(Index(WKST,0))) {
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* Store(0, Index(WKST,1))
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* } else {
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* Store(Arg0, Index(WKST,1))
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* }
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*/
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Return(WKST)
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} /* End Method(\_WAK) */
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@ -0,0 +1,114 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* SMBUS Support */
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Mutex (SBX0, 0x00)
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OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
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Field (SMB0, ByteAcc, NoLock, Preserve) {
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HSTS, 8, /* SMBUS status */
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SSTS, 8, /* SMBUS slave status */
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HCNT, 8, /* SMBUS control */
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HCMD, 8, /* SMBUS host cmd */
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HADD, 8, /* SMBUS address */
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DAT0, 8, /* SMBUS data0 */
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DAT1, 8, /* SMBUS data1 */
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BLKD, 8, /* SMBUS block data */
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SCNT, 8, /* SMBUS slave control */
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SCMD, 8, /* SMBUS shaow cmd */
|
||||
SEVT, 8, /* SMBUS slave event */
|
||||
SDAT, 8 /* SMBUS slave data */
|
||||
}
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||||
|
||||
Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
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||||
Store (0x1E, HSTS)
|
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Store (0xFA, Local0)
|
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While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
|
||||
Stall (0x64)
|
||||
Decrement (Local0)
|
||||
}
|
||||
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
Method (SWTC, 1, NotSerialized) {
|
||||
Store (Arg0, Local0)
|
||||
Store (0x07, Local2)
|
||||
Store (One, Local1)
|
||||
While (LEqual (Local1, One)) {
|
||||
Store (And (HSTS, 0x1E), Local3)
|
||||
If (LNotEqual (Local3, Zero)) { /* read sucess */
|
||||
If (LEqual (Local3, 0x02)) {
|
||||
Store (Zero, Local2)
|
||||
}
|
||||
|
||||
Store (Zero, Local1)
|
||||
}
|
||||
Else {
|
||||
If (LLess (Local0, 0x0A)) { /* read failure */
|
||||
Store (0x10, Local2)
|
||||
Store (Zero, Local1)
|
||||
}
|
||||
Else {
|
||||
Sleep (0x0A) /* 10 ms, try again */
|
||||
Subtract (Local0, 0x0A, Local0)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Return (Local2)
|
||||
}
|
||||
|
||||
Method (SMBR, 3, NotSerialized) {
|
||||
Store (0x07, Local0)
|
||||
If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
|
||||
Store (WCLR (), Local0) /* clear SMBUS status register before read data */
|
||||
If (LEqual (Local0, Zero)) {
|
||||
Release (SBX0)
|
||||
Return (0x0)
|
||||
}
|
||||
|
||||
Store (0x1F, HSTS)
|
||||
Store (Or (ShiftLeft (Arg1, One), One), HADD)
|
||||
Store (Arg2, HCMD)
|
||||
If (LEqual (Arg0, 0x07)) {
|
||||
Store (0x48, HCNT) /* read byte */
|
||||
}
|
||||
|
||||
Store (SWTC (0x03E8), Local1) /* 1000 ms */
|
||||
If (LEqual (Local1, Zero)) {
|
||||
If (LEqual (Arg0, 0x07)) {
|
||||
Store (DAT0, Local0)
|
||||
}
|
||||
}
|
||||
Else {
|
||||
Store (Local1, Local0)
|
||||
}
|
||||
|
||||
Release (SBX0)
|
||||
}
|
||||
|
||||
/* DBGO("the value of SMBusData0 register ") */
|
||||
/* DBGO(Arg2) */
|
||||
/* DBGO(" is ") */
|
||||
/* DBGO(Local0) */
|
||||
/* DBGO("\n") */
|
||||
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* No SuperIO device or functionality yet */
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* THERMAL */
|
||||
Scope(\_TZ) {
|
||||
Name (KELV, 2732)
|
||||
Name (THOT, 800)
|
||||
Name (TCRT, 850)
|
||||
|
||||
ThermalZone(TZ00) {
|
||||
Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
|
||||
/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
|
||||
Return(Add(0, 2730))
|
||||
}
|
||||
Method(_AL0,0) { /* Returns package of cooling device to turn on */
|
||||
/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
|
||||
Return(Package() {\_TZ.TZ00.FAN0})
|
||||
}
|
||||
Device (FAN0) {
|
||||
Name(_HID, EISAID("PNP0C0B"))
|
||||
Name(_PR0, Package() {PFN0})
|
||||
}
|
||||
|
||||
PowerResource(PFN0,0,0) {
|
||||
Method(_STA) {
|
||||
Store(0xF,Local0)
|
||||
Return(Local0)
|
||||
}
|
||||
Method(_ON) {
|
||||
/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
|
||||
}
|
||||
Method(_OFF) {
|
||||
/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
|
||||
}
|
||||
}
|
||||
|
||||
Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
|
||||
/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
|
||||
Return (Add (THOT, KELV))
|
||||
}
|
||||
Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
|
||||
/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
|
||||
Return (Add (TCRT, KELV))
|
||||
}
|
||||
Method(_TMP,0) { /* return current temp of this zone */
|
||||
Store (SMBR (0x07, 0x4C,, 0x00), Local0)
|
||||
If (LGreater (Local0, 0x10)) {
|
||||
Store (Local0, Local1)
|
||||
}
|
||||
Else {
|
||||
Add (Local0, THOT, Local0)
|
||||
Return (Add (400, KELV))
|
||||
}
|
||||
|
||||
Store (SMBR (0x07, 0x4C, 0x01), Local0)
|
||||
/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
|
||||
/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
|
||||
If (LGreater (Local0, 0x10)) {
|
||||
If (LGreater (Local0, Local1)) {
|
||||
Store (Local0, Local1)
|
||||
}
|
||||
|
||||
Multiply (Local1, 10, Local1)
|
||||
Return (Add (Local1, KELV))
|
||||
}
|
||||
Else {
|
||||
Add (Local0, THOT, Local0)
|
||||
Return (Add (400 , KELV))
|
||||
}
|
||||
} /* end of _TMP */
|
||||
} /* end of TZ00 */
|
||||
}
|
||||
|
|
@ -25,6 +25,19 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
|||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* USB overcurrent mapping pins. */
|
||||
Name(UOM0, 0)
|
||||
Name(UOM1, 2)
|
||||
Name(UOM2, 0)
|
||||
Name(UOM3, 7)
|
||||
Name(UOM4, 2)
|
||||
Name(UOM5, 2)
|
||||
Name(UOM6, 6)
|
||||
Name(UOM7, 2)
|
||||
Name(UOM8, 6)
|
||||
Name(UOM9, 6)
|
||||
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue