mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB
Make code more readable. Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc. BUG=N/A TEST=build Change-Id: I5d84e575935e9e60610e1805e1402f290672b114 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
parent
9484792ad1
commit
8d98d80e53
|
@ -9,7 +9,7 @@ chip soc/intel/braswell
|
||||||
register "PcdMrcInitMmioSize" = "0x0800"
|
register "PcdMrcInitMmioSize" = "0x0800"
|
||||||
register "PcdMrcInitSpdAddr1" = "0xa0"
|
register "PcdMrcInitSpdAddr1" = "0xa0"
|
||||||
register "PcdMrcInitSpdAddr2" = "0xa2"
|
register "PcdMrcInitSpdAddr2" = "0xa2"
|
||||||
register "PcdIgdDvmt50PreAlloc" = "1"
|
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB"
|
||||||
register "PcdApertureSize" = "2"
|
register "PcdApertureSize" = "2"
|
||||||
register "PcdGttSize" = "1"
|
register "PcdGttSize" = "1"
|
||||||
register "PcdDvfsEnable" = "0"
|
register "PcdDvfsEnable" = "0"
|
||||||
|
|
Loading…
Reference in New Issue