soc/amd/common/lpc: Skip SERIRQ setup when using eSPI
BUG=b:157984427 TEST=check value of PMx054 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2ca14c137ed784a1a7cfeed969719f46fc8230f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -25,6 +25,18 @@
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/* Most systems should have already enabled the bridge */
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void __weak soc_late_lpc_bridge_enable(void) { }
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static void setup_serirq(void)
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{
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u8 byte;
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/* Set up SERIRQ, enable continuous mode */
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byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE);
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if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
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byte |= PM_SERIRQ_MODE;
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pm_write8(PM_SERIRQ_CONF, byte);
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}
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static void lpc_init(struct device *dev)
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{
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u8 byte;
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@ -81,12 +93,8 @@ static void lpc_init(struct device *dev)
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/* Initialize i8254 timers */
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setup_i8254();
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/* Set up SERIRQ, enable continuous mode */
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byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE);
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if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
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byte |= PM_SERIRQ_MODE;
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pm_write8(PM_SERIRQ_CONF, byte);
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if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
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setup_serirq();
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}
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static void lpc_read_resources(struct device *dev)
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