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soc/amd/common/lpc: Skip SERIRQ setup when using eSPI 

BUG=b:157984427
TEST=check value of PMx054

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I2ca14c137ed784a1a7cfeed969719f46fc8230f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Marshall Dawson 2020-06-29 17:56:02 -06:00
parent 2099716f69
commit 8d9b878f63
1 changed files with 14 additions and 6 deletions
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20
src/soc/amd/common/block/lpc/lpc.c
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@ -25,6 +25,18 @@
/* Most systems should have already enabled the bridge */ /* Most systems should have already enabled the bridge */
void __weak soc_late_lpc_bridge_enable(void) { } void __weak soc_late_lpc_bridge_enable(void) { }
static void setup_serirq(void)
{
u8 byte;
/* Set up SERIRQ, enable continuous mode */
byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE);
if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
byte |= PM_SERIRQ_MODE;
pm_write8(PM_SERIRQ_CONF, byte);
}
static void lpc_init(struct device *dev) static void lpc_init(struct device *dev)
{ {
u8 byte; u8 byte;
@ -81,12 +93,8 @@ static void lpc_init(struct device *dev)
/* Initialize i8254 timers */ /* Initialize i8254 timers */
setup_i8254(); setup_i8254();
/* Set up SERIRQ, enable continuous mode */ if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE); setup_serirq();
if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
byte |= PM_SERIRQ_MODE;
pm_write8(PM_SERIRQ_CONF, byte);
} }
static void lpc_read_resources(struct device *dev) static void lpc_read_resources(struct device *dev)