vc/intel/fsp2/denverton_ns: Remove unused files
The Denverton-NS SoC uses the header files from the FSP git repository. Therefore, remove these from coreboot source. Change-Id: Ib22d3f5e5ce83eb83bf589ea8bba7b55ebe44ea8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47754 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
Michael Niewöhner
parent
5c186c6777
commit
8db0a22677
5 changed files with 0 additions and 1157 deletions
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@ -511,7 +511,6 @@ M: David Guckian <david.guckian@intel.com>
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S: Odd Fixes
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F: src/mainboard/intel/harcuvar/
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F: src/soc/intel/denverton_ns/
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F: src/vendorcode/intel/fsp/fsp2_0/denverton_ns/
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INTEL FSP 1.1
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M: Lee Leahy <leroy.p.leahy@intel.com>
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@ -1,48 +0,0 @@
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/** @file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
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||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#include <FspEas.h>
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#pragma pack(1)
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#define FSPT_UPD_SIGNATURE 0x545F445055564E44 /* 'DNVUPD_T' */
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#define FSPM_UPD_SIGNATURE 0x4D5F445055564E44 /* 'DNVUPD_M' */
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#define FSPS_UPD_SIGNATURE 0x535F445055564E44 /* 'DNVUPD_S' */
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#pragma pack()
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#endif
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@ -1,710 +0,0 @@
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/** @file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
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||||
list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPMUPD_H__
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#define __FSPMUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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#define MAX_CH 2 /* Maximum Number of Memory Channels */
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#define MAX_DIMM 2 /* Maximum Number of DIMMs PER Memory Channel */
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#define MAX_SPD_BYTES 512 /* Maximum Number of SPD bytes */
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/*
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* Memory Down structures.
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*/
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typedef enum {
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STATE_MEMORY_SLOT = 0, /* No memory down and a physical memory slot. */
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STATE_MEMORY_DOWN = 1, /* Memory down and not a physical memory slot. */
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} MemorySlotState;
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typedef struct {
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MemorySlotState SlotState[MAX_CH][MAX_DIMM]; /* Memory Down state of
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each DIMM in each
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Channel */
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UINT16 SpdDataLen; /* Length in Bytes of a single DIMM's SPD Data */
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UINT8 *SpdDataPtr[MAX_CH][MAX_DIMM]; /* Pointer to SPD Data for each
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DIMM in each Channel */
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} MEMORY_DOWN_CONFIG;
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/*
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* SMBIOS Memory Info structures.
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*/
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typedef struct {
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UINT8 DimmId;
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UINT32 SizeInMb;
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UINT16 MfgId;
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UINT8
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ModulePartNum[20]; /* Module part number for DDR3 is 18 bytes
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however for DRR4 20 bytes as per JEDEC Spec,
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so reserving 20 bytes */
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} DIMM_INFO;
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typedef struct {
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UINT8 ChannelId;
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UINT8 DimmCount;
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DIMM_INFO DimmInfo[MAX_DIMM];
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} CHANNEL_INFO;
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typedef struct {
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UINT8 Revision;
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UINT16 DataWidth;
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/** As defined in SMBIOS 3.0 spec
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Section 7.18.2 and Table 75
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**/
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UINT8 MemoryType;
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UINT16 MemoryFrequencyInMHz;
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/** As defined in SMBIOS 3.0 spec
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Section 7.17.3 and Table 72
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**/
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UINT8 ErrorCorrectionType;
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UINT8 ChannelCount;
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CHANNEL_INFO ChannelInfo[MAX_CH];
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} FSP_SMBIOS_MEMORY_INFO;
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/*
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* GBE PCD supported states.
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*/
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typedef enum {
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BL_GBE0_GBE1_DISABLED,
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BL_GBE0_GBE1_ENABLED,
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BL_GBE1_DISABLED,
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} BL_GBE_PCD_STATE;
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/*
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* FIA MUX configuration structures.
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*/
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#define BL_ME_FIA_MUX_LANE_NUM_MAX 20
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#define BL_ME_FIA_MUX_LANE_NUM_MIN 1
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#define BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH 2
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#define BL_ME_FIA_MUX_LANE_MUX_SEL_MASK 0x3
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#define BL_ME_FIA_MUX_LANE_XHCI_ONLY 0xFF00000000
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typedef enum {
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BL_FIA_LANE00 = 0,
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BL_FIA_LANE01,
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BL_FIA_LANE02,
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BL_FIA_LANE03,
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BL_FIA_LANE04,
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BL_FIA_LANE05,
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BL_FIA_LANE06,
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BL_FIA_LANE07,
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BL_FIA_LANE08,
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BL_FIA_LANE09,
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BL_FIA_LANE10,
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BL_FIA_LANE11,
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BL_FIA_LANE12,
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BL_FIA_LANE13,
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BL_FIA_LANE14,
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BL_FIA_LANE15,
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BL_FIA_LANE16,
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BL_FIA_LANE17,
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BL_FIA_LANE18,
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BL_FIA_LANE19,
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} BL_ME_FIA_MUX_LANE_ORDER;
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#define BL_ME_FIA_MUX_LANE_SATA0_BEGING BL_FIA_LANE04
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#define BL_ME_FIA_MUX_LANE_SATA1_BEGING BL_FIA_LANE12
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#define BL_FIA_LANE_CONFIG(Config, Lane) \
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((UINT64)((UINT64)(Config) \
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<< ((UINT64)(Lane) * (BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH))))
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typedef union _BL_ME_FIA_MUX_CONFIG {
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UINT64 MeFiaMuxLaneConfig;
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struct {
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UINT64 Lane00MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE
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UINT64 Lane01MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE
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UINT64 Lane02MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE
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UINT64 Lane03MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE
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UINT64 Lane04MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane05MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane06MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane07MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane08MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane09MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane10MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane11MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane12MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane13MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane14MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane15MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or
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// SATA
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UINT64 Lane16MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or
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// SATA
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UINT64 Lane17MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or
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// SATA
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UINT64 Lane18MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or
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// SATA
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UINT64 Lane19MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or
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// SATA
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UINT64 Reserved : 24;
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} BL_MeFiaMuxLaneMuxSel;
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} BL_ME_FIA_MUX_CONFIG;
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typedef enum {
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BL_ME_FIA_MUX_LANE_DISCONNECTED,
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BL_ME_FIA_MUX_LANE_PCIE,
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BL_ME_FIA_MUX_LANE_SATA,
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BL_ME_FIA_MUX_LANE_XHCI,
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} BL_ME_FIA_MUX_LANE_CONFIG;
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#define BL_ME_FIA_SATA_LANE_SEL_WIDTH 2
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#define BL_ME_FIA_SATA_LANE_XHCI_ONLY 0x55000000
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typedef enum {
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BL_FIA_SATA_LANE04 = 0,
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BL_FIA_SATA_LANE05,
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BL_FIA_SATA_LANE06,
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BL_FIA_SATA_LANE07,
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BL_FIA_SATA_LANE08,
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BL_FIA_SATA_LANE09,
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BL_FIA_SATA_LANE10,
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BL_FIA_SATA_LANE11,
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BL_FIA_SATA_LANE12,
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BL_FIA_SATA_LANE13,
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BL_FIA_SATA_LANE14,
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BL_FIA_SATA_LANE15,
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BL_FIA_SATA_LANE16,
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BL_FIA_SATA_LANE17,
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BL_FIA_SATA_LANE18,
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BL_FIA_SATA_LANE19
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} BL_ME_FIA_SATA_LANE_ORDER;
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#define BL_FIA_SATA_LANE_CONFIG(Config, Lane) \
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((UINT32)((UINT32)(Config) \
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<< ((UINT32)(Lane) * (BL_ME_FIA_SATA_LANE_SEL_WIDTH))))
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typedef union _BL_ME_FIA_SATA_CONFIG {
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UINT64 MeFiaSataLaneConfig;
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struct {
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UINT64 Lane04SataSel : 2;
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UINT64 Lane05SataSel : 2;
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UINT64 Lane06SataSel : 2;
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UINT64 Lane07SataSel : 2;
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UINT64 Lane08SataSel : 2;
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UINT64 Lane09SataSel : 2;
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UINT64 Lane10SataSel : 2;
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UINT64 Lane11SataSel : 2;
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UINT64 Lane12SataSel : 2;
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UINT64 Lane13SataSel : 2;
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UINT64 Lane14SataSel : 2;
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UINT64 Lane15SataSel : 2;
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UINT64 Lane16SataSel : 2;
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UINT64 Lane17SataSel : 2;
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UINT64 Lane18SataSel : 2;
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UINT64 Lane19SataSel : 2;
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UINT64 Reserved : 32;
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} BL_MeFiaSataLaneSataSel;
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} BL_ME_FIA_SATA_CONFIG;
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typedef enum {
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BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED = 0,
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BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED = 1,
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BL_ME_FIA_SATA_CONTROLLER_LANE_SS_AND_GPIO_ASSIGNED = 3
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} BL_ME_FIA_SATA_LANE_CONFIG;
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#define BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH 4
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#define BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH 8
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#define BL_ME_FIA_PCIE_ROOT_CONFIG_XHCI_ONLY 0x0
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typedef enum {
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BL_FIA_PCIE_ROOT_PORT_0 = 0,
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BL_FIA_PCIE_ROOT_PORT_1,
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BL_FIA_PCIE_ROOT_PORT_2,
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BL_FIA_PCIE_ROOT_PORT_3,
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BL_FIA_PCIE_ROOT_PORT_4,
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BL_FIA_PCIE_ROOT_PORT_5,
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BL_FIA_PCIE_ROOT_PORT_6,
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BL_FIA_PCIE_ROOT_PORT_7
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} BL_ME_FIA_PCIE_ROOT_PORT_ORDER;
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#define BL_FIA_PCIE_ROOT_PORT_CONFIG(Type, Config, PcieRootPort) \
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(((Type) == BL_ME_FIA_PCIE_ROOT_PORT_STATE) \
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? ((UINT64)((UINT64)(Config) << (UINT64)(PcieRootPort))) \
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: ((UINT64)( \
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(UINT64)(Config) << (UINT64)( \
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((UINT64)(PcieRootPort) * \
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(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH)) + \
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BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH))))
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|
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typedef union _BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG {
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UINT64 MeFiaPcieRootPortsConfig;
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struct {
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UINT64 PcieRp0En : 1;
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UINT64 PcieRp1En : 1;
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UINT64 PcieRp2En : 1;
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UINT64 PcieRp3En : 1;
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UINT64 PcieRp4En : 1;
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UINT64 PcieRp5En : 1;
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UINT64 PcieRp6En : 1;
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UINT64 PcieRp7En : 1;
|
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UINT64 PcieRp0LinkWidth : 4;
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UINT64 PcieRp1LinkWidth : 4;
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UINT64 PcieRp2LinkWidth : 4;
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UINT64 PcieRp3LinkWidth : 4;
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UINT64 PcieRp4LinkWidth : 4;
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UINT64 PcieRp5LinkWidth : 4;
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UINT64 PcieRp6LinkWidth : 4;
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UINT64 PcieRp7LinkWidth : 4;
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UINT64 Reserved : 24;
|
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} BL_MeFiaPcieRpConfig;
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} BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG;
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|
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typedef enum {
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BL_ME_FIA_PCIE_ROOT_PORT_STATE,
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BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH
|
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} BL_ME_FIA_PCIE_ROOT_PORT_CONFIG_TYPE;
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|
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typedef enum {
|
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BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,
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BL_ME_FIA_PCIE_ROOT_PORT_ENABLED
|
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} BL_ME_FIA_PCIE_ROOT_PORT_STATE_CONFIG;
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|
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typedef enum {
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BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL = 0,
|
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BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1 = 0xF
|
||||
} BL_ME_FIA_PCIE_ROOT_PORT_LINK_CONFIG;
|
||||
|
||||
typedef struct _BL_ME_FIA_CONFIG {
|
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BL_ME_FIA_MUX_CONFIG MuxConfiguration;
|
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BL_ME_FIA_SATA_CONFIG SataLaneConfiguration;
|
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BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG PcieRootPortsConfiguration;
|
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} BL_ME_FIA_CONFIG;
|
||||
|
||||
/*
|
||||
* The FIA_MUX_CONFIG block describes the expected configuration of
|
||||
* FIA MUX configuration.
|
||||
*/
|
||||
typedef struct {
|
||||
UINT32 SkuNumLanesAllowed; // Platform view of Num Lanes allowed
|
||||
BL_ME_FIA_CONFIG FiaMuxConfig; // Current Platform FIA MUX Configuration
|
||||
BL_ME_FIA_CONFIG FiaMuxConfigRequest; // FIA MUX Configuration Requested
|
||||
} BL_FIA_MUX_CONFIG;
|
||||
|
||||
/*
|
||||
* The FIA_MUX_CONFIG_STATUS describes the status of configuring
|
||||
* FIA MUX configuration.
|
||||
*/
|
||||
typedef struct {
|
||||
UINT64 FiaMuxConfigGetStatus; // Status returned from FiaMuxConfigGet,
|
||||
// if not EFI_SUCCESS, then error occurred
|
||||
// and user can decide on next steps
|
||||
UINT64 FiaMuxConfigSetStatus; // Status returned from FiaMuxConfigSet,
|
||||
// if not EFI_SUCCESS, then error occurred
|
||||
// and user can decide on next steps
|
||||
BOOLEAN FiaMuxConfigSetRequired; // Boolean: true - a FiaMuxConfigSet
|
||||
// was required, false otherwise
|
||||
} BL_FIA_MUX_CONFIG_STATUS;
|
||||
|
||||
/*
|
||||
* FIA MUX Config HOB structure
|
||||
*/
|
||||
typedef struct {
|
||||
BL_FIA_MUX_CONFIG FiaMuxConfig;
|
||||
BL_FIA_MUX_CONFIG_STATUS FiaMuxConfigStatus;
|
||||
} BL_FIA_MUX_CONFIG_HOB;
|
||||
|
||||
/* PCIe port bifurcation codes - matches setup option values */
|
||||
#define PCIE_BIF_CTRL_x2x2x2x2 0
|
||||
#define PCIE_BIF_CTRL_x2x2x4 1
|
||||
#define PCIE_BIF_CTRL_x4x2x2 2
|
||||
#define PCIE_BIF_CTRL_x4x4 3
|
||||
#define PCIE_BIF_CTRL_x8 4
|
||||
|
||||
#define BL_MAX_PCIE_CTRL 2
|
||||
|
||||
/*
|
||||
* HSIO INFORMATION structure
|
||||
*/
|
||||
typedef enum {
|
||||
BL_SKU_HSIO_06 = 6,
|
||||
BL_SKU_HSIO_08 = 8,
|
||||
BL_SKU_HSIO_10 = 10,
|
||||
BL_SKU_HSIO_12 = 12,
|
||||
BL_SKU_HSIO_20 = 20,
|
||||
} BL_SKU_HSIO_LANE_NUMBER;
|
||||
|
||||
typedef struct {
|
||||
UINT16 NumLanesSupported;
|
||||
UINT8 PcieBifCtr[BL_MAX_PCIE_CTRL];
|
||||
BL_ME_FIA_CONFIG FiaConfig;
|
||||
} BL_HSIO_INFORMATION;
|
||||
|
||||
/*
|
||||
* eMMC DLL structure for EMMC DLL registers settings
|
||||
*/
|
||||
typedef struct {
|
||||
UINT32 TxCmdCntl;
|
||||
UINT32 TxDataCntl1;
|
||||
UINT32 TxDataCntl2;
|
||||
UINT32 RxCmdDataCntl1;
|
||||
UINT32 RxStrobeCntl;
|
||||
UINT32 RxCmdDataCntl2;
|
||||
UINT32 MasterSwCntl;
|
||||
} BL_EMMC_DLL_CONFIG;
|
||||
|
||||
typedef struct {
|
||||
UINT16 Signature;
|
||||
BL_EMMC_DLL_CONFIG eMMCDLLConfig;
|
||||
} BL_EMMC_INFORMATION;
|
||||
|
||||
typedef enum {
|
||||
BL_FAST_BOOT_CHECKER_NORMAL = 0,
|
||||
BL_FAST_BOOT_CHECKER_WARNING,
|
||||
BL_FAST_BOOT_CHECKER_CRITICAL
|
||||
} BL_FAST_BOOT_CHECKER;
|
||||
|
||||
#define BL_MAX_SCRUB_SEGMENTS 5
|
||||
|
||||
typedef struct {
|
||||
UINT16 Start; // Determines the low range for a memory segment (in MB)
|
||||
UINT16 End; // Determines the high range for a memory segment (in MB)
|
||||
} BL_SCRUB_SEGMENT;
|
||||
|
||||
typedef struct {
|
||||
UINT8 NumberOfSegments;
|
||||
UINT8 Reserved;
|
||||
BL_SCRUB_SEGMENT ScrubSegment[BL_MAX_SCRUB_SEGMENTS];
|
||||
} BL_MEMORY_SCRUB_SEGMENTS;
|
||||
|
||||
/** Fsp M Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0040 - Tseg Size
|
||||
Size of SMRAM memory reserved.
|
||||
2:2 MB, 4:4 MB, 8:8 MB, 16:16 MB
|
||||
**/
|
||||
UINT8 PcdSmmTsegSize;
|
||||
|
||||
/** Offset 0x0041 - FSP Debug Print Level
|
||||
Select the FSP debug message print level.
|
||||
0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG
|
||||
**/
|
||||
UINT8 PcdFspDebugPrintErrorLevel;
|
||||
|
||||
/** Offset 0x0042 - Channel 0 DIMM 0 SPD SMBus Address
|
||||
SPD SMBus Address of each DIMM slot.
|
||||
**/
|
||||
UINT8 PcdSpdSmbusAddress_0_0;
|
||||
|
||||
/** Offset 0x0043 - Channel 0 DIMM 1 SPD SMBus Address
|
||||
SPD SMBus Address of each DIMM slot.
|
||||
**/
|
||||
UINT8 PcdSpdSmbusAddress_0_1;
|
||||
|
||||
/** Offset 0x0044 - Channel 1 DIMM 0 SPD SMBus Address
|
||||
SPD SMBus Address of each DIMM slot.
|
||||
**/
|
||||
UINT8 PcdSpdSmbusAddress_1_0;
|
||||
|
||||
/** Offset 0x0045 - Channel 1 DIMM 1 SPD SMBus Address
|
||||
SPD SMBus Address of each DIMM slot.
|
||||
**/
|
||||
UINT8 PcdSpdSmbusAddress_1_1;
|
||||
|
||||
/** Offset 0x0046 - Enable Rank Margin Tool
|
||||
Enable/disable Rank Margin Tool.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdMrcRmtSupport;
|
||||
|
||||
/** Offset 0x0047 - RMT CPGC exp_loop_cnt
|
||||
Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1).
|
||||
1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12,
|
||||
13:13, 14:14, 15:15
|
||||
**/
|
||||
UINT8 PcdMrcRmtCpgcExpLoopCntValue;
|
||||
|
||||
/** Offset 0x0048 - RMT CPGC num_bursts
|
||||
Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1).
|
||||
1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12,
|
||||
13:13, 14:14, 15:15
|
||||
**/
|
||||
UINT8 PcdMrcRmtCpgcNumBursts;
|
||||
|
||||
/** Offset 0x0049 - Preserve Memory Across Reset
|
||||
Enable/disable memory preservation across reset.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdMemoryPreservation;
|
||||
|
||||
/** Offset 0x004A - Fast Boot
|
||||
Enable/disable Fast Boot function. Once enabled, all following boots
|
||||
will use the
|
||||
presaved MRC data to improve the boot performance.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdFastBoot;
|
||||
|
||||
/** Offset 0x004B - ECC Support
|
||||
Enable/disable ECC Support.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdEccSupport;
|
||||
|
||||
/** Offset 0x004C - HSUART Device
|
||||
Select the PCI High Speed UART Device for Serial Port.
|
||||
0:HSUART0, 1:HSUART1, 2:HSUART2
|
||||
**/
|
||||
UINT8 PcdHsuartDevice;
|
||||
|
||||
/** Offset 0x004D - Memory Down
|
||||
Enable/disable Memory Down function.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdMemoryDown;
|
||||
|
||||
/** Offset 0x004E
|
||||
**/
|
||||
UINT32 PcdMemoryDownConfigPtr;
|
||||
|
||||
/** Offset 0x0052 - SATA Controller 0
|
||||
Enable/disable SATA Controller 0.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdEnableSATA0;
|
||||
|
||||
/** Offset 0x0053 - SATA Controller 1
|
||||
Enable/disable SATA Controller 1.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdEnableSATA1;
|
||||
|
||||
/** Offset 0x0054 - Intel Quick Assist Technology
|
||||
Enable/disable Intel Quick Assist Technology.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdEnableIQAT;
|
||||
|
||||
/** Offset 0x0055 - SPD Write Disable
|
||||
Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 =
|
||||
[FORCE_DISABLE])
|
||||
0:Force Enable, 1:Force Disable
|
||||
**/
|
||||
UINT8 PcdSmbusSpdWriteDisable;
|
||||
|
||||
/** Offset 0x0056 - ME_SHUTDOWN Message
|
||||
Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP
|
||||
Integration Guide
|
||||
for details.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdEnableMeShutdown;
|
||||
|
||||
/** Offset 0x0057 - XHCI Controller
|
||||
Enable / Disable XHCI controller
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdEnableXhci;
|
||||
|
||||
/** Offset 0x0058 - Memory Frequency
|
||||
Set DDR Memory Frequency, refer to FSP Integration Guide for details.
|
||||
15:Auto, 3:1600, 4:1866, 5:2133, 6:2400
|
||||
**/
|
||||
UINT8 PcdDdrFreq;
|
||||
|
||||
/** Offset 0x0059 - MMIO Size
|
||||
Set memory mapped IO space size
|
||||
0:2048M, 1:1024M, 2:3072M
|
||||
**/
|
||||
UINT8 PcdMmioSize;
|
||||
|
||||
/** Offset 0x005A - ME HECI Communication
|
||||
Enable/Disable ME HECI communication
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdMeHeciCommunication;
|
||||
|
||||
/** Offset 0x005B - HSIO Lanes Number
|
||||
HSIO lanes number of SKU
|
||||
6:6, 8:8, 10:10, 12:12, 20:20
|
||||
**/
|
||||
UINT8 PcdHsioLanesNumber;
|
||||
|
||||
/** Offset 0x005C
|
||||
**/
|
||||
UINT32 PcdFiaMuxConfigPtr;
|
||||
|
||||
/** Offset 0x0060 - Customer Revision
|
||||
The Customer can set this revision string for their own purpose.
|
||||
**/
|
||||
UINT8 PcdCustomerRevision[32];
|
||||
|
||||
/** Offset 0x0080 - 32-Bit bus mode
|
||||
Enable/Disable 32-Bit bus memory mode.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdHalfWidthEnable;
|
||||
|
||||
/** Offset 0x0081 - TCL Performance
|
||||
Enable/Disable Tcl timing for performance.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdTclIdle;
|
||||
|
||||
/** Offset 0x0082 - Interleave Mode
|
||||
Select Interleave Mode
|
||||
0:DISABLED, 1:MODE0, 2:MODE1, 3:MODE2
|
||||
**/
|
||||
UINT8 PcdInterleaveMode;
|
||||
|
||||
/** Offset 0x0083 - Memory Thermal Throttling
|
||||
Enable/disable Memory Thermal Throttling management mode
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdMemoryThermalThrottling;
|
||||
|
||||
/** Offset 0x0084 - Memory Test
|
||||
Enable / Disable Memory Test, refer to FSP Integration Guide for
|
||||
details.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdSkipMemoryTest;
|
||||
|
||||
/** Offset 0x0085
|
||||
**/
|
||||
BL_MEMORY_SCRUB_SEGMENTS *PcdScrubSegmentPtr;
|
||||
|
||||
/** Offset 0x0089 - USB2 Port 1 OC Pin
|
||||
Map selected OC pin to the port
|
||||
0:OC Pin 0, 8:No pin mapped
|
||||
**/
|
||||
UINT8 PcdUsb2Port1Pin;
|
||||
|
||||
/** Offset 0x008A - USB2 Port 2 OC Pin
|
||||
Map selected OC pin to the port
|
||||
0:OC Pin 0, 8:No pin mapped
|
||||
**/
|
||||
UINT8 PcdUsb2Port2Pin;
|
||||
|
||||
/** Offset 0x008B - USB2 Port 3 OC Pin
|
||||
Map selected OC pin to the port
|
||||
0:OC Pin 0, 8:No pin mapped
|
||||
**/
|
||||
UINT8 PcdUsb2Port3Pin;
|
||||
|
||||
/** Offset 0x008C - USB2 Port 4 OC Pin
|
||||
Map selected OC pin to the port
|
||||
0:OC Pin 0, 8:No pin mapped
|
||||
**/
|
||||
UINT8 PcdUsb2Port4Pin;
|
||||
|
||||
/** Offset 0x008D - USB3 Port 1 OC Pin
|
||||
Map selected OC pin to the port
|
||||
0:OC Pin 0, 8:No pin mapped
|
||||
**/
|
||||
UINT8 PcdUsb3Port1Pin;
|
||||
|
||||
/** Offset 0x008E - USB3 Port 2 OC Pin
|
||||
Map selected OC pin to the port
|
||||
0:OC Pin 0, 8:No pin mapped
|
||||
**/
|
||||
UINT8 PcdUsb3Port2Pin;
|
||||
|
||||
/** Offset 0x008F - USB3 Port 3 OC Pin
|
||||
Map selected OC pin to the port
|
||||
0:OC Pin 0, 8:No pin mapped
|
||||
**/
|
||||
UINT8 PcdUsb3Port3Pin;
|
||||
|
||||
/** Offset 0x0090 - USB3 Port 4 OC Pin
|
||||
Map selected OC pin to the port
|
||||
0:OC Pin 0, 8:No pin mapped
|
||||
**/
|
||||
UINT8 PcdUsb3Port4Pin;
|
||||
|
||||
/** Offset 0x0091 - IOxAPIC 0-199
|
||||
Enable/disable IOxAPIC 24-119 entries
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdIOxAPIC0_199;
|
||||
|
||||
/** Offset 0x0092 - DMAP_X16
|
||||
Enable/Disable DMAP_X16 dynamic MRC field indicating memory device
|
||||
width is x16 or not
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdDmapX16;
|
||||
|
||||
/** Offset 0x0093
|
||||
**/
|
||||
UINT8 UnusedUpdSpace0[333];
|
||||
|
||||
/** Offset 0x01E0
|
||||
**/
|
||||
UINT8 ReservedMemoryInitUpd[16];
|
||||
} FSP_M_CONFIG;
|
||||
|
||||
/** Fsp M UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSPM_ARCH_UPD FspmArchUpd;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
FSP_M_CONFIG FspmConfig;
|
||||
|
||||
/** Offset 0x01F0
|
||||
**/
|
||||
UINT8 UnusedUpdSpace1[14];
|
||||
|
||||
/** Offset 0x01FE
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPM_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
@ -1,289 +0,0 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPSUPD_H__
|
||||
#define __FSPSUPD_H__
|
||||
|
||||
#include <FspUpd.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
/** Fsp S Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0020 - PCIe Controller 0 Bifurcation
|
||||
Configure PCI Express controller 0 bifurcation.
|
||||
0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
|
||||
**/
|
||||
UINT8 PcdBifurcationPcie0;
|
||||
|
||||
/** Offset 0x0021 - PCIe Controller 1 Bifurcation
|
||||
Configure PCI Express controller 1 bifurcation.
|
||||
0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8
|
||||
**/
|
||||
UINT8 PcdBifurcationPcie1;
|
||||
|
||||
/** Offset 0x0022 - Active Core Count
|
||||
Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores)
|
||||
0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11,
|
||||
12:12, 13:13,
|
||||
14:14, 15:15
|
||||
**/
|
||||
UINT8 PcdActiveCoreCount;
|
||||
|
||||
/** Offset 0x0023
|
||||
**/
|
||||
UINT32 PcdCpuMicrocodePatchBase;
|
||||
|
||||
/** Offset 0x0027
|
||||
**/
|
||||
UINT32 PcdCpuMicrocodePatchSize;
|
||||
|
||||
/** Offset 0x002B - PCIe Controller 0
|
||||
Enable / Disable PCI Express controller 0
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdEnablePcie0;
|
||||
|
||||
/** Offset 0x002C - PCIe Controller 1
|
||||
Enable / Disable PCI Express controller 1
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdEnablePcie1;
|
||||
|
||||
/** Offset 0x002D - Embedded Multi-Media Controller (eMMC)
|
||||
Enable / Disable Embedded Multi-Media controller
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PcdEnableEmmc;
|
||||
|
||||
/** Offset 0x002E - LAN Controllers
|
||||
Enable / Disable LAN controllers, refer to FSP Integration Guide for
|
||||
details.
|
||||
0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
|
||||
**/
|
||||
UINT8 PcdEnableGbE;
|
||||
|
||||
/** Offset 0x002F
|
||||
**/
|
||||
UINT32 PcdFiaMuxConfigRequestPtr;
|
||||
|
||||
/** Offset 0x0033
|
||||
**/
|
||||
UINT8 UnusedUpdSpace0[4];
|
||||
|
||||
/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis
|
||||
Desired DeEmphasis level for PCIE root port
|
||||
0:6dB, 1:3.5dB
|
||||
**/
|
||||
UINT8 PcdPcieRootPort0DeEmphasis;
|
||||
|
||||
/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis
|
||||
Desired DeEmphasis level for PCIE root port
|
||||
0:6dB, 1:3.5dB
|
||||
**/
|
||||
UINT8 PcdPcieRootPort1DeEmphasis;
|
||||
|
||||
/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis
|
||||
Desired DeEmphasis level for PCIE root port
|
||||
0:6dB, 1:3.5dB
|
||||
**/
|
||||
UINT8 PcdPcieRootPort2DeEmphasis;
|
||||
|
||||
/** Offset 0x003A - PCIe Root Port 3 DeEmphasis
|
||||
Desired DeEmphasis level for PCIE root port
|
||||
0:6dB, 1:3.5dB
|
||||
**/
|
||||
UINT8 PcdPcieRootPort3DeEmphasis;
|
||||
|
||||
/** Offset 0x003B - PCIe Root Port 4 DeEmphasis
|
||||
Desired DeEmphasis level for PCIE root port
|
||||
0:6dB, 1:3.5dB
|
||||
**/
|
||||
UINT8 PcdPcieRootPort4DeEmphasis;
|
||||
|
||||
/** Offset 0x003C - PCIe Root Port 5 DeEmphasis
|
||||
Desired DeEmphasis level for PCIE root port
|
||||
0:6dB, 1:3.5dB
|
||||
**/
|
||||
UINT8 PcdPcieRootPort5DeEmphasis;
|
||||
|
||||
/** Offset 0x003D - PCIe Root Port 6 DeEmphasis
|
||||
Desired DeEmphasis level for PCIE root port
|
||||
0:6dB, 1:3.5dB
|
||||
**/
|
||||
UINT8 PcdPcieRootPort6DeEmphasis;
|
||||
|
||||
/** Offset 0x003E - PCIe Root Port 7 DeEmphasis
|
||||
Desired DeEmphasis level for PCIE root port
|
||||
0:6dB, 1:3.5dB
|
||||
**/
|
||||
UINT8 PcdPcieRootPort7DeEmphasis;
|
||||
|
||||
/** Offset 0x003F
|
||||
**/
|
||||
UINT8 UnusedUpdSpace1;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
UINT32 PcdEMMCDLLConfigPtr;
|
||||
|
||||
/** Offset 0x0044 - PCIe Root Port 0 Link Speed
|
||||
Upper limit on link operational speed for PCI Express RootPort
|
||||
1:GEN1, 2:GEN2, 3:GEN3
|
||||
**/
|
||||
UINT8 PcdPcieRootPort0LinkSpeed;
|
||||
|
||||
/** Offset 0x0045 - PCIe Root Port 1 Link Speed
|
||||
Upper limit on link operational speed for PCI Express RootPort
|
||||
1:GEN1, 2:GEN2, 3:GEN3
|
||||
**/
|
||||
UINT8 PcdPcieRootPort1LinkSpeed;
|
||||
|
||||
/** Offset 0x0046 - PCIe Root Port 2 Link Speed
|
||||
Upper limit on link operational speed for PCI Express RootPort
|
||||
1:GEN1, 2:GEN2, 3:GEN3
|
||||
**/
|
||||
UINT8 PcdPcieRootPort2LinkSpeed;
|
||||
|
||||
/** Offset 0x0047 - PCIe Root Port 3 Link Speed
|
||||
Upper limit on link operational speed for PCI Express RootPort
|
||||
1:GEN1, 2:GEN2, 3:GEN3
|
||||
**/
|
||||
UINT8 PcdPcieRootPort3LinkSpeed;
|
||||
|
||||
/** Offset 0x0048 - PCIe Root Port 4 Link Speed
|
||||
Upper limit on link operational speed for PCI Express RootPort
|
||||
1:GEN1, 2:GEN2, 3:GEN3
|
||||
**/
|
||||
UINT8 PcdPcieRootPort4LinkSpeed;
|
||||
|
||||
/** Offset 0x0049 - PCIe Root Port 5 Link Speed
|
||||
Upper limit on link operational speed for PCI Express RootPort
|
||||
1:GEN1, 2:GEN2, 3:GEN3
|
||||
**/
|
||||
UINT8 PcdPcieRootPort5LinkSpeed;
|
||||
|
||||
/** Offset 0x004A - PCIe Root Port 6 Link Speed
|
||||
Upper limit on link operational speed for PCI Express RootPort
|
||||
1:GEN1, 2:GEN2, 3:GEN3
|
||||
**/
|
||||
UINT8 PcdPcieRootPort6LinkSpeed;
|
||||
|
||||
/** Offset 0x004B - PCIe Root Port 7 Link Speed
|
||||
Upper limit on link operational speed for PCI Express RootPort
|
||||
1:GEN1, 2:GEN2, 3:GEN3
|
||||
**/
|
||||
UINT8 PcdPcieRootPort7LinkSpeed;
|
||||
|
||||
/** Offset 0x004C - PCIe Root Port 0 ASPM
|
||||
Enable PCI Express Active State Power Management settings
|
||||
0:Disabled, 2:L1
|
||||
**/
|
||||
UINT8 PcdPcieRootPort0Aspm;
|
||||
|
||||
/** Offset 0x004D - PCIe Root Port 1 ASPM
|
||||
Enable PCI Express Active State Power Management settings
|
||||
0:Disabled, 2:L1
|
||||
**/
|
||||
UINT8 PcdPcieRootPort1Aspm;
|
||||
|
||||
/** Offset 0x004E - PCIe Root Port 2 ASPM
|
||||
Enable PCI Express Active State Power Management settings
|
||||
0:Disabled, 2:L1
|
||||
**/
|
||||
UINT8 PcdPcieRootPort2Aspm;
|
||||
|
||||
/** Offset 0x004F - PCIe Root Port 3 ASPM
|
||||
Enable PCI Express Active State Power Management settings
|
||||
0:Disabled, 2:L1
|
||||
**/
|
||||
UINT8 PcdPcieRootPort3Aspm;
|
||||
|
||||
/** Offset 0x0050 - PCIe Root Port 4 ASPM
|
||||
Enable PCI Express Active State Power Management settings
|
||||
0:Disabled, 2:L1
|
||||
**/
|
||||
UINT8 PcdPcieRootPort4Aspm;
|
||||
|
||||
/** Offset 0x0051 - PCIe Root Port 5 ASPM
|
||||
Enable PCI Express Active State Power Management settings
|
||||
0:Disabled, 2:L1
|
||||
**/
|
||||
UINT8 PcdPcieRootPort5Aspm;
|
||||
|
||||
/** Offset 0x0052 - PCIe Root Port 6 ASPM
|
||||
Enable PCI Express Active State Power Management settings
|
||||
0:Disabled, 2:L1
|
||||
**/
|
||||
UINT8 PcdPcieRootPort6Aspm;
|
||||
|
||||
/** Offset 0x0053 - PCIe Root Port 7 ASPM
|
||||
Enable PCI Express Active State Power Management settings
|
||||
0:Disabled, 2:L1
|
||||
**/
|
||||
UINT8 PcdPcieRootPort7Aspm;
|
||||
|
||||
/** Offset 0x0054
|
||||
**/
|
||||
UINT8 UnusedUpdSpace2[140];
|
||||
|
||||
/** Offset 0x00E0
|
||||
**/
|
||||
UINT8 ReservedSiliconInitUpd[16];
|
||||
} FSP_S_CONFIG;
|
||||
|
||||
/** Fsp S UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSP_S_CONFIG FspsConfig;
|
||||
|
||||
/** Offset 0x00F0
|
||||
**/
|
||||
UINT8 UnusedUpdSpace3[14];
|
||||
|
||||
/** Offset 0x00FE
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPS_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
@ -1,109 +0,0 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPTUPD_H__
|
||||
#define __FSPTUPD_H__
|
||||
|
||||
#include <FspUpd.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
/** Fsp T Core UPD
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
UINT32 MicrocodeRegionBase;
|
||||
|
||||
/** Offset 0x0024
|
||||
**/
|
||||
UINT32 MicrocodeRegionLength;
|
||||
|
||||
/** Offset 0x0028
|
||||
**/
|
||||
UINT32 CodeRegionBase;
|
||||
|
||||
/** Offset 0x002C
|
||||
**/
|
||||
UINT32 CodeRegionLength;
|
||||
|
||||
/** Offset 0x0030
|
||||
**/
|
||||
UINT8 Reserved1[16];
|
||||
} FSPT_CORE_UPD;
|
||||
|
||||
/** Fsp T Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0040 - Disable Port80 output in FSP-T
|
||||
Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output,
|
||||
2:Disable Port80
|
||||
Output, refer to FSP Integration Guide for details
|
||||
0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
|
||||
**/
|
||||
UINT8 PcdFsptPort80RouteDisable;
|
||||
|
||||
/** Offset 0x0041
|
||||
**/
|
||||
UINT8 ReservedTempRamInitUpd[31];
|
||||
} FSPT_CONFIG;
|
||||
|
||||
/** Fsp T UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSPT_CORE_UPD FsptCoreUpd;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
FSPT_CONFIG FsptConfig;
|
||||
|
||||
/** Offset 0x0060
|
||||
**/
|
||||
UINT8 UnusedUpdSpace0[30];
|
||||
|
||||
/** Offset 0x007E
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPT_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue