From 8db77d71bbbb872831a6bb61dac249d551773a84 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 30 Aug 2021 18:20:34 +0200 Subject: [PATCH] soc/amd/*: move reset_i2c_peripherals call after early GPIO setup Since bootblock_soc_early_init gets called before bootblock_mainboard_early_init which does the early GPIO setup, external I2C level shifters that are controlled by GPIOs might not be enabled yet. Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure that the early GPIO setup is already done when reset_i2c_peripherals is called. Haven't probed any SCL signal on the non-SoC side of the I2C level shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a barla/careena Chromebook doesn't have the longer than expected SCL pulses any more. Signed-off-by: Felix Held Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57291 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/early_fch.c | 2 +- src/soc/amd/mendocino/early_fch.c | 2 +- src/soc/amd/picasso/early_fch.c | 2 +- src/soc/amd/stoneyridge/bootblock.c | 11 ++++++----- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 027a0b54bf..586e80cbd0 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -51,7 +51,6 @@ void fch_pre_init(void) fch_enable_legacy_io(); fch_disable_legacy_dma_io(); enable_aoac_devices(); - reset_i2c_peripherals(); /* * On reset Range_0 defaults to enabled. We want to start with a clean @@ -70,6 +69,7 @@ void fch_pre_init(void) /* After console init */ void fch_early_init(void) { + reset_i2c_peripherals(); pm_set_power_failure_state(); fch_print_pmxc0_status(); i2c_soc_early_init(); diff --git a/src/soc/amd/mendocino/early_fch.c b/src/soc/amd/mendocino/early_fch.c index fe68421949..d37b45d9ff 100644 --- a/src/soc/amd/mendocino/early_fch.c +++ b/src/soc/amd/mendocino/early_fch.c @@ -53,7 +53,6 @@ void fch_pre_init(void) fch_enable_legacy_io(); fch_disable_legacy_dma_io(); enable_aoac_devices(); - reset_i2c_peripherals(); /* * On reset Range_0 defaults to enabled. We want to start with a clean @@ -72,6 +71,7 @@ void fch_pre_init(void) /* After console init */ void fch_early_init(void) { + reset_i2c_peripherals(); pm_set_power_failure_state(); fch_print_pmxc0_status(); i2c_soc_early_init(); diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index f7435aae3d..d0c10f2589 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -60,7 +60,6 @@ void fch_pre_init(void) fch_enable_cf9_io(); fch_enable_legacy_io(); enable_aoac_devices(); - reset_i2c_peripherals(); /* * On reset Range_0 defaults to enabled. We want to start with a clean @@ -79,6 +78,7 @@ void fch_pre_init(void) /* After console init */ void fch_early_init(void) { + reset_i2c_peripherals(); pm_set_power_failure_state(); fch_print_pmxc0_status(); i2c_soc_early_init(); diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 8c6fde521a..66b22be99e 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -95,6 +95,12 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) } void bootblock_soc_early_init(void) +{ + bootblock_fch_early_init(); + post_code(0x90); +} + +void bootblock_soc_init(void) { /* * This call (sb_reset_i2c_peripherals) was originally early at @@ -105,12 +111,7 @@ void bootblock_soc_early_init(void) * just pauses but we don't know why. */ reset_i2c_peripherals(); - bootblock_fch_early_init(); - post_code(0x90); -} -void bootblock_soc_init(void) -{ if (CONFIG(AMD_SOC_CONSOLE_UART)) assert(CONFIG_UART_FOR_CONSOLE >= 0 && CONFIG_UART_FOR_CONSOLE <= 1);