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amd/stoneyridge: Clarify XHCI_PM register definitions 

Change-Id: I1b44ffd7c0244b0408c3823d634a9b8d5038462f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Marshall Dawson 2018-10-05 16:08:51 -06:00 committed by Martin Roth
parent 1548458efd
commit 8db8432cf5
1 changed files with 16 additions and 17 deletions
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5
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -279,11 +279,10 @@
#define PWR_RESET_CFG 0x10
#define TOGGLE_ALL_PWR_GOOD BIT(1)
/* XHCI_PM Registers: 0xfed81c00 */
#define XHCI_PM_INDIRECT_INDEX 0x48
#define XHCI_PM_INDIRECT_DATA 0x4c
#define XHCI_OVER_CURRENT_CONTROL 0x30
#define EHCI_OVER_CURRENT_CONTROL 0x70
#define USB_OC0 0
#define USB_OC1 1
#define USB_OC2 2
@ -294,12 +293,12 @@
#define USB_OC7 7
#define USB_OC_DISABLE 0xf
#define USB_OC_DISABLE_ALL 0xffff
#define OC_PORT0_SHIFT 0
#define OC_PORT1_SHIFT 4
#define OC_PORT2_SHIFT 8
#define OC_PORT3_SHIFT 12
#define EHCI_OVER_CURRENT_CONTROL 0x70
#define EHCI_HUB_CONFIG4 0x90
#define DEBUG_PORT_SELECT_SHIFT 16
#define DEBUG_PORT_ENABLE BIT(18)