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soc/intel/common/dmi: Add support for locking down SRL 

This change adds support to lock down the DMI configuration
in dmi_lockdown_cfg() by setting Secure Register Lock (SRL)
bit in DMI control register.

BUG=b:171534504

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48258
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik 2020-12-02 17:20:24 -08:00 committed by Furquan Shaikh
parent 876b422641
commit 8dcd62d705
2 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/common/block/include/intelblocks/dmi.h
View File

@ -8,6 +8,9 @@
#define PCR_DMI_DMICTL 0x2234
#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
#define PCR_DMI_GCS 0x274C
#define PCR_DMI_GCS_BILD (1 << 0)
/*
* Takes base, size and destination ID and configures the GPMR
* for accessing the region.

10
src/soc/intel/common/pch/lockdown/lockdown.c
View File

@ -2,6 +2,7 @@
#include <bootstate.h>
#include <intelblocks/cfg.h>
#include <intelblocks/dmi.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/pcr.h>
#include <intelpch/lockdown.h>
@ -9,9 +10,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
#define PCR_DMI_GCS 0x274C
#define PCR_DMI_GCS_BILD (1 << 0)
/*
* This function will get lockdown config specific to soc.
*
@ -40,6 +38,12 @@ static void dmi_lockdown_cfg(void)
* "1b": LPC/eSPI
*/
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
/*
* Set Secure Register Lock (SRL) bit in DMI control register to lock
* DMI configuration.
*/
pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK);
}
static void fast_spi_lockdown_cfg(int chipset_lockdown)