cbfs_spi: Enable speed logging by default for BIOS_DEBUG
The SPI transfer speed logging in cbfs_spi is super useful, doesn't get in the way (just adding one line per stage, essentially) and should have no notable overhead. Let's enable it by default for the BIOS_DEBUG log level rather than having to recompile to get it. Also fix an issue with building this code on MIPS due to lack of 64-bit division primitives. (This means MIPS and arm32 board may display incorrect results when reading more than 4MB in a single transfer, which sounds very unlikely.) Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -31,21 +31,18 @@ static struct spi_flash spi_flash_info;
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static bool spi_flash_init_done;
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/*
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* Set this to 1 to debug SPI speed, 0 to disable it
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* The format is:
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* SPI speed logging for big transfers available with BIOS_DEBUG. The format is:
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*
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* read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps
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* read SPI 0x62854 0x7db7: 10416 us, 3089 KB/s, 24.712 Mbps
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*
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* The important number is the last one. It should roughly match your SPI
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* clock. If it doesn't, your driver might need a little tuning.
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*/
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#define SPI_SPEED_DEBUG 0
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static ssize_t spi_readat(const struct region_device *rd, void *b,
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size_t offset, size_t size)
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{
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struct stopwatch sw;
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bool show = SPI_SPEED_DEBUG && size >= 4 * KiB;
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bool show = size >= 4 * KiB && console_log_level(BIOS_DEBUG);
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if (show)
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stopwatch_init(&sw);
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@ -58,7 +55,7 @@ static ssize_t spi_readat(const struct region_device *rd, void *b,
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u64 speed; /* KiB/s */
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int bps; /* Bits per second */
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speed = (u64)size * 1000 / usecs;
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speed = size * 1000 / usecs;
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bps = speed * 8;
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printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n",
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