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mb/siemens/mc_ehl1: Adjust PCIe settings in devicetree 

This board does not use CLKREQ-signaling for PCIe, so disable the pin
assignments. In addition only three clock outputs are used for PCIe,
therefore disable all others to improve EMI.

Change-Id: I545f890fa55a109df7f44d2c82170874fb769009
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56455
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh 2021-07-20 14:07:02 +02:00 committed by Patrick Georgi
parent 3ee18cefa3
commit 8dd1a54f09
1 changed files with 8 additions and 8 deletions
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16
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
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@ -50,18 +50,18 @@ chip soc/intel/elkhartlake
register "PcieRpEnable[6]" = "1" register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "0x00" register "PcieClkSrcUsage[0]" = "0x00"
register "PcieClkSrcUsage[1]" = "0x06" register "PcieClkSrcUsage[1]" = "0x01"
register "PcieClkSrcUsage[2]" = "0x04" register "PcieClkSrcUsage[2]" = "0x02"
register "PcieClkSrcUsage[3]" = "0xFF" register "PcieClkSrcUsage[3]" = "0xFF"
register "PcieClkSrcUsage[4]" = "0xFF" register "PcieClkSrcUsage[4]" = "0xFF"
register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcUsage[5]" = "0xFF"
register "PcieClkSrcClkReq[0]" = "0x0" register "PcieClkSrcClkReq[0]" = "0xFF"
register "PcieClkSrcClkReq[1]" = "0x1" register "PcieClkSrcClkReq[1]" = "0xFF"
register "PcieClkSrcClkReq[2]" = "0x2" register "PcieClkSrcClkReq[2]" = "0xFF"
register "PcieClkSrcClkReq[3]" = "0x3" register "PcieClkSrcClkReq[3]" = "0xFF"
register "PcieClkSrcClkReq[4]" = "0x4" register "PcieClkSrcClkReq[4]" = "0xFF"
register "PcieClkSrcClkReq[5]" = "0x5" register "PcieClkSrcClkReq[5]" = "0xFF"
# Storage (SATA/SDCARD/EMMC) related UPDs # Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"