mb/asus/p8z77-series: Add P8Z77-V as a variant of P8Z77 series
Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Bill XIE
Patrick Georgi
parent
e395cf926a
commit
8dd8f66807
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# ASUS P8Z77-V
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This page describes how to run coreboot on the [ASUS P8Z77-V].
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## Flashing coreboot
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```eval_rst
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+---------------------+----------------+
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| Type | Value |
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+=====================+================+
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| Socketed flash | yes |
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+---------------------+----------------+
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| Model | W25Q64FVA1Q |
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+---------------------+----------------+
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| Size | 8 MiB |
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+---------------------+----------------+
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| Package | DIP-8 |
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+---------------------+----------------+
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| Write protection | yes |
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+---------------------+----------------+
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| Dual BIOS feature | no |
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+---------------------+----------------+
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| Internal flashing | no |
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+---------------------+----------------+
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```
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The flash IC is located between the black and white PCI Express x16 slots (circled):
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### How to flash
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The main SPI flash cannot be written because the vendor firmware disables BIOSWE
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and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external
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programmer is required. You must flash standalone, flashing in-circuit doesn't
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work. The flash chip is socketed, so it's easy to remove and reflash.
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## Working
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- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.28
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- Integrated Ethernet NIC
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- S3 Suspend to RAM
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- USB2 on rear and front panel connectors
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- USB3 (Z77's and ASMedia's works)
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- Integrated SATA of Z77
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- Integrated SATA of ASM1061 (works under GNU/Linux but not under SeaBIOS)
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- CPU Temp sensors (tested PSensor on GNU/Linux)
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- TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12)
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- Native raminit
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- Integrated graphics with libgfxinit (VGA/DVI-D/HDMI tested and working)
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- PCIe in PCIe-16x/8x slots (tested using an S3 Matrix GPU)
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- Debug output from serial port
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- Atheros AR9485 half-height mini PCIe WNIC adapted with Wi-Fi Go! Adapter
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- Default PCIe config (PCIEX_16_3 as 1x, PCIe Port 4 to ASM1061 SATA, see below
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for other potential options)
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## Untested
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- EHCI debugging
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- S/PDIF audio
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- PS/2 mouse
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## Not working
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- PCIEX_1_2 (expected under default PCIe config)
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- Other PCIe configs (see below)
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## PCIe config
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On Asus vendor firmware, other than the default config already supported here,
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there remain another two configs: "PCIEX_16_3 as x4, with PCIEX_1_1, PCIEX_1_2
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and onboard ASM1061 disabled" and "PCIEX_16_3 as x1, but PCIe Port 4 to PCIEX_1_2,
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with onboard ASM1061 disabled".
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Configuring PCIEX_16_3 as x4 needs to program 0x3 to the LSB of PCHSTRP9, but
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also needs to configure GPIOs in the Super I/O chip different than the default
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config in this board's override tree.
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Configuring PCIe Port 4 to PCIEX_1_2 needs to configure GPIOs in the Super I/O
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chip differently than the default config.
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I have tried a lot, but sadly I am unable to produce the same result as the vendor
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firmware.
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## Asus Wi-Fi Go!
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Asus Wi-Fi Go! has several versions. P8Z77-V has the earliest version.
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See [Asus Wi-Fi Go! v1].
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | bd82x6x |
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+------------------+--------------------------------------------------+
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| CPU | model_206ax |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6779D |
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+------------------+--------------------------------------------------+
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| EC | None |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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## Extra resources
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- [Flash chip datasheet][W25Q64FVA1Q]
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[ASUS P8Z77-V]: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/
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[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[Asus Wi-Fi Go! v1]: ./wifigo_v1.md
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@ -0,0 +1,40 @@
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# Asus Wi-Fi Go! v1
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In this version, a standard half-length mPCIe card is mounted on the Asus Wi-Fi
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Go! daughter board, and the daughter board is connected to the motherboard
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through a proprietary 16-1 pin connector.
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I managed to grope the most pinout of the proprietary connector.
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See [Mini PCIe pinout] for more info.
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```eval_rst
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+------------+----------+-----------+------------+----------+-----------+
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| WIFIGO Pin | Usage | mPCIe pin | WIFIGO Pin | Usage | mPCIe pin |
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+============+==========+===========+============+==========+===========+
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| 1 | 3.3v | (many) | 2 | REFCLK- | 11 |
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+------------+----------+-----------+------------+----------+-----------+
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| 3 | GND | (many) | 4 | REFCLK+ | 13 |
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+------------+----------+-----------+------------+----------+-----------+
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| 5 | WAKE# | 1 | 6 | PERn0 | 23 |
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+------------+----------+-----------+------------+----------+-----------+
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| 7 | (absent) | | 8 | PERp0 | 25 |
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+------------+----------+-----------+------------+----------+-----------+
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| 9 | GND | | 10 | PETn0 | 31 |
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+------------+----------+-----------+------------+----------+-----------+
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| 11 | PERST# | 20 | 12 | PETp0 | 33 |
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+------------+----------+-----------+------------+----------+-----------+
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| 13 | GND | | 14 | (USBD-?) | (36?) |
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+------------+----------+-----------+------------+----------+-----------+
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| 15 | 3.3v | | 16 | (USBD+?) | (38?) |
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+------------+----------+-----------+------------+----------+-----------+
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```
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There are two kinds of daughter boards using this connector. One among them has
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one MMCX antenna connector, the other has two antenna connectors and USB lane
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wired (this kind may be called BT Go!). I can only obtain the former, so I
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cannot confirm the exact way the USB data lane gets wired.
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## Extra resources
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[Mini PCIe pinout]: https://pinoutguide.com/Slots/mini_pcie_pinout.shtml
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@ -22,6 +22,7 @@ This section contains documentation about coreboot on specific mainboards.
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- [P8H61-M LX](asus/p8h61-m_lx.md)
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- [P8H61-M Pro](asus/p8h61-m_pro.md)
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- [P8Z77-M Pro](asus/p8z77-m_pro.md)
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- [P8Z77-V](asus/p8z77-v.md)
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## Cavium
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@ -23,11 +23,13 @@ config VARIANT_DIR
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string
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default "p8z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO
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default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2
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default "p8z77-v" if BOARD_ASUS_P8Z77_V
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config MAINBOARD_PART_NUMBER
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string
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default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO
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default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2
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default "P8Z77-V" if BOARD_ASUS_P8Z77_V
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config OVERRIDE_DEVICETREE
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string
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@ -13,3 +13,13 @@ config BOARD_ASUS_P8Z77_V_LX2
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select REALTEK_8168_RESET
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select SUPERIO_NUVOTON_NCT6779D
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select USE_NATIVE_RAMINIT
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config BOARD_ASUS_P8Z77_V
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bool "P8Z77-V"
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select BOARD_ASUS_P8Z77_SERIES
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select BOARD_ROMSIZE_KB_8192
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select DRIVERS_ASMEDIA_ASPM_BLACKLIST # for ASM1061 eSATA
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_USES_IFD_GBE_REGION
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select SUPERIO_NUVOTON_NCT6779D
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select USE_NATIVE_RAMINIT
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@ -0,0 +1,7 @@
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Category: desktop
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Board URL: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/
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ROM package: DIP-8
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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Release year: 2013
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boot_option=Fallback
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debug_level=Debug
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nmi=Disable
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power_on_after_fail=Disable
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sata_mode=AHCI
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gfx_uma_size=64M
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 2 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 3 debug_level
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 4 power_on_after_fail
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411 2 e 5 sata_mode
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# coreboot config options: northbridge
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416 5 e 6 gfx_uma_size
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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# Generic on/off enum
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1 0 Disable
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1 1 Enable
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# boot_option
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2 0 Fallback
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2 1 Normal
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# debug_level
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3 0 Emergency
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3 1 Alert
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3 2 Critical
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3 3 Error
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3 4 Warning
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3 5 Notice
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3 6 Info
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3 7 Debug
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3 8 Spew
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# power_on_after_fail
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4 0 Disable
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4 1 Enable
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4 2 Keep
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# sata_mode
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5 0 AHCI
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5 1 Compatible
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5 2 Legacy
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# gfx_uma_size (Intel IGP Video RAM size)
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6 0 32M
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6 1 64M
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6 2 96M
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6 3 128M
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6 4 160M
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6 5 192M
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6 6 224M
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6 7 256M
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6 8 288M
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6 9 320M
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6 10 352M
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6 11 384M
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6 12 416M
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6 13 448M
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6 14 480M
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6 15 512M
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6 16 1024M
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# -----------------------------------------------------------------
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checksums
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checksum 392 423 984
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct6779d/nct6779d.h>
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#define GLOBAL_DEV PNP_DEV(0x2e, 0)
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#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
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#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 2, 0 },
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{ 1, 2, 0 },
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{ 1, 2, 1 },
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{ 1, 0, 1 },
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{ 1, 0, 2 },
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{ 1, 2, 2 },
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{ 1, 2, 3 },
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{ 1, 2, 3 },
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{ 1, 2, 4 },
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{ 1, 0, 4 },
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{ 1, 2, 6 },
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{ 1, 2, 5 },
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{ 1, 2, 5 },
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{ 1, 2, 6 },
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};
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void bootblock_mainboard_early_init(void)
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{
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nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
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/* Select SIO pin states */
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pnp_write_config(GLOBAL_DEV, 0x1a, 0x00);
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pnp_write_config(GLOBAL_DEV, 0x2a, 0x40);
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pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
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/* Power RAM in S3 */
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pnp_set_logical_device(ACPI_DEV);
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pnp_write_config(ACPI_DEV, 0xe4, 0x10);
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nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
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/* Enable UART */
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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read_spd(&spd[0], 0x50, id_only);
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read_spd(&spd[1], 0x51, id_only);
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read_spd(&spd[2], 0x52, id_only);
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read_spd(&spd[3], 0x53, id_only);
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}
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@ -0,0 +1,19 @@
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-- SPDX-License-Identifier: GPL-2.0-or-later
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(DP1,
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HDMI1,
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HDMI2,
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HDMI3,
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Analog,
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others => Disabled);
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end GMA.Mainboard;
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@ -0,0 +1,181 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO,
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.gpio1 = GPIO_MODE_GPIO,
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.gpio2 = GPIO_MODE_NATIVE,
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.gpio3 = GPIO_MODE_NATIVE,
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.gpio4 = GPIO_MODE_NATIVE,
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.gpio5 = GPIO_MODE_NATIVE,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_NATIVE,
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.gpio10 = GPIO_MODE_NATIVE,
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.gpio11 = GPIO_MODE_NATIVE,
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.gpio12 = GPIO_MODE_NATIVE,
|
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.gpio13 = GPIO_MODE_GPIO,
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.gpio14 = GPIO_MODE_NATIVE,
|
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_GPIO,
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.gpio17 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_NATIVE,
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||||
.gpio19 = GPIO_MODE_NATIVE,
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.gpio20 = GPIO_MODE_NATIVE,
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.gpio21 = GPIO_MODE_NATIVE,
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.gpio22 = GPIO_MODE_GPIO,
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.gpio23 = GPIO_MODE_NATIVE,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_NATIVE,
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.gpio26 = GPIO_MODE_NATIVE,
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||||
.gpio27 = GPIO_MODE_GPIO,
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||||
.gpio28 = GPIO_MODE_GPIO,
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||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
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||||
.gpio31 = GPIO_MODE_GPIO,
|
||||
};
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||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
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||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
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||||
.gpio8 = GPIO_DIR_INPUT,
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||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
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||||
.gpio16 = GPIO_DIR_INPUT,
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||||
.gpio17 = GPIO_DIR_INPUT,
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.gpio22 = GPIO_DIR_INPUT,
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||||
.gpio24 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_INPUT,
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||||
.gpio28 = GPIO_DIR_OUTPUT,
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||||
.gpio29 = GPIO_DIR_OUTPUT,
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.gpio31 = GPIO_DIR_OUTPUT,
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||||
};
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||||
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||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
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||||
.gpio15 = GPIO_LEVEL_LOW,
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.gpio24 = GPIO_LEVEL_LOW,
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||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
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||||
.gpio31 = GPIO_LEVEL_HIGH,
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};
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||||
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||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
};
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||||
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||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio1 = GPIO_INVERT,
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||||
.gpio8 = GPIO_INVERT,
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||||
.gpio13 = GPIO_INVERT,
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||||
};
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||||
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||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_NATIVE,
|
||||
.gpio36 = GPIO_MODE_NATIVE,
|
||||
.gpio37 = GPIO_MODE_NATIVE,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_NATIVE,
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_NATIVE,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_NATIVE,
|
||||
.gpio51 = GPIO_MODE_NATIVE,
|
||||
.gpio52 = GPIO_MODE_NATIVE,
|
||||
.gpio53 = GPIO_MODE_NATIVE,
|
||||
.gpio54 = GPIO_MODE_NATIVE,
|
||||
.gpio55 = GPIO_MODE_NATIVE,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_NATIVE,
|
||||
.gpio61 = GPIO_MODE_NATIVE,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
.gpio48 = GPIO_DIR_OUTPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio48 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_NATIVE,
|
||||
.gpio71 = GPIO_MODE_NATIVE,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */
|
||||
0x104384fb, /* Subsystem ID */
|
||||
15, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x104384fb),
|
||||
AZALIA_PIN_CFG(0, 0x11, 0x99430140),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x01011012),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x01016011),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x01012014),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x01456130),
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
|
||||
0x80862806, /* Codec Vendor / Device ID: Intel HDMI */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
AZALIA_PIN_CFG(3, 0x05, 0x58560010),
|
||||
AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/intel/sandybridge
|
||||
device domain 0 on
|
||||
subsystemid 0x1043 0x84ca inherit
|
||||
device pci 01.1 on end # PCIEX_16_2
|
||||
chip southbridge/intel/bd82x6x
|
||||
register "gen1_dec" = "0x000c0291"
|
||||
|
||||
device pci 19.0 on end # Intel Gigabit Ethernet
|
||||
device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 (electrical x1 or x4)
|
||||
device pci 1c.1 on end # PCIe Port 2 PCIEX_1_1
|
||||
device pci 1c.3 on end # PCIe Port 4 ASM1061 SATA or PCIEX_1_2
|
||||
device pci 1c.4 on end # PCIe Port 5 ASM1083 PCI Bridge
|
||||
device pci 1c.6 on end # PCIe Port 7 Wi-Fi Go!
|
||||
device pci 1c.7 on end # PCIe Port 8 ASM1042 USB3
|
||||
|
||||
device pci 1f.0 on # LPC bridge
|
||||
chip superio/nuvoton/nct6779d
|
||||
device pnp 2e.1 off end # Parallel
|
||||
device pnp 2e.2 on # UART A
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off end # UART B, IR
|
||||
device pnp 2e.5 on # PS2 KBC
|
||||
io 0x60 = 0x0060 # KBC1 base
|
||||
io 0x62 = 0x0064 # KBC2 base
|
||||
irq 0x70 = 1 # Keyboard IRQ
|
||||
irq 0x72 = 12 # Mouse IRQ
|
||||
|
||||
# KBC 12Mhz/A20 speed/sw KBRST
|
||||
drq 0xf0 = 0x82
|
||||
end
|
||||
device pnp 2e.6 off end # CIR
|
||||
device pnp 2e.7 off end # GPIOs 6-8
|
||||
device pnp 2e.8 off end # WDT1 GPIO 0-1
|
||||
device pnp 2e.108 on end # GPIO0-1
|
||||
device pnp 2e.109 on end # GPIO1
|
||||
device pnp 2e.209 on # GPIO2
|
||||
drq 0xe0 = 0xdf
|
||||
end
|
||||
device pnp 2e.309 on end # GPIO3
|
||||
device pnp 2e.509 on # GPIO5
|
||||
drq 0xf4 = 0xfc
|
||||
end
|
||||
device pnp 2e.a on # ACPI
|
||||
drq 0xe3 = 0x04 # Thermal shutdown event issued
|
||||
drq 0xe7 = 0x11 # Enable 3VSBS to power RAM on S3
|
||||
drq 0xf2 = 0x5d # Enable PME
|
||||
end
|
||||
device pnp 2e.b on # H/W Monitor, FP LED
|
||||
io 0x60 = 0x290
|
||||
io 0x62 = 0
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 2e.d off end # WDT1
|
||||
device pnp 2e.e off end # CIR wake-up
|
||||
device pnp 2e.f on # Push-pull/Open-drain
|
||||
drq 0xe4 = 0xfc # GP5 PP
|
||||
drq 0xe6 = 0x7f # GP7 PP
|
||||
end
|
||||
device pnp 2e.14 off end # Port 80 UART
|
||||
device pnp 2e.16 off end # Deep sleep
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp c31.0 on end # TPM
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue