From 8dffc38f6e8ff4d1f7e26b261bfd6d7fda6be173 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Mon, 7 Dec 2020 20:48:09 +0530 Subject: [PATCH] mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs Add support to pick the right vbt from cbfs according to SKU-ID. Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533 Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/intel/adlrvp/Makefile.inc | 5 +++++ src/mainboard/intel/adlrvp/mainboard.c | 15 +++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 75c8cf8e20..12f546b2e3 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -19,6 +19,11 @@ ramstage-y += mainboard.c ramstage-y += board_id.c ramstage-y += gpio.c +ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y) +$(call add_vbt_to_cbfs, vbt_lp5.bin, 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(VARIANT_DIR)/vbt_lp5.bin) +$(call add_vbt_to_cbfs, vbt_ddr5.bin, 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(VARIANT_DIR)/vbt_ddr5.bin) +endif + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index fb2557836a..39462040fe 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -38,3 +39,17 @@ struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, }; + +const char *mainboard_vbt_filename(void) +{ + uint8_t sku_id = get_board_id(); + switch (sku_id) { + case ADL_P_LP5_1: + case ADL_P_LP5_2: + return "vbt_lp5.bin"; + case ADL_P_DDR5: + return "vbt_ddr5.bin"; + default: + return "vbt.bin"; + } +}