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AGESA f15: Remove f10 references 

Vendorcode for f15 also has f10 support, so
AMD_AGESA_FAMILY_10 was never selected.

Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki 2017-08-24 11:10:50 +03:00
parent 7a10c9b106
commit 8e0bc131c8
13 changed files with 24 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/agesa/family15/romstage.c
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@ -24,7 +24,7 @@
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include "northbridge/amd/agesa/family10/reset_test.h"
#include "northbridge/amd/agesa/family15/reset_test.h"
#include <nb_cimx.h>
#include <sb_cimx.h>

5
src/mainboard/amd/dinar/rd890_cfg.h
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@ -28,11 +28,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define DEFAULT_HT_PATH {0x0, 0x1}
#else /* FAMILY10 */
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#endif

9
src/mainboard/supermicro/h8qgi/buildOpts.c
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@ -425,13 +425,4 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
* This file include MUST occur AFTER the user option selection settings
*/
/*
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
#endif
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#endif
*/
#include "MaranelloInstall.h"

5
src/mainboard/supermicro/h8qgi/rd890_cfg.h
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@ -27,11 +27,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define DEFAULT_HT_PATH {0x0, 0x1}
#else /* FAMILY10 */
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#endif

2
src/mainboard/supermicro/h8qgi/romstage.c
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@ -25,7 +25,7 @@
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/family10/reset_test.h>
#include <northbridge/amd/agesa/family15/reset_test.h>
#include <nb_cimx.h>
#include <sb_cimx.h>
#include <superio/nuvoton/wpcm450/wpcm450.h>

5
src/mainboard/supermicro/h8scm/rd890_cfg.h
View File

@ -27,11 +27,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define DEFAULT_HT_PATH {0x0, 0x1}
#else /* FAMILY10 */
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#endif

2
src/mainboard/supermicro/h8scm/romstage.c
View File

@ -25,7 +25,7 @@
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/family10/reset_test.h>
#include <northbridge/amd/agesa/family15/reset_test.h>
#include <nb_cimx.h>
#include <sb_cimx.h>
#include <superio/nuvoton/wpcm450/wpcm450.h>

9
src/mainboard/tyan/s8226/buildOpts.c
View File

@ -425,13 +425,4 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
* This file include MUST occur AFTER the user option selection settings
*/
/*
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
#endif
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#endif
*/
#include "SanMarinoInstall.h"

5
src/mainboard/tyan/s8226/rd890_cfg.h
View File

@ -27,11 +27,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define DEFAULT_HT_PATH {0x0, 0x1}
#else /* FAMILY10 */
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#endif

2
src/mainboard/tyan/s8226/romstage.c
View File

@ -25,7 +25,7 @@
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/family10/reset_test.h>
#include <northbridge/amd/agesa/family15/reset_test.h>
#include <nb_cimx.h>
#include <sb_cimx.h>
#include <superio/winbond/common/winbond.h>

0
src/northbridge/amd/agesa/family10/amdfam10.h → src/northbridge/amd/agesa/family15/amdfam10.h
View File

0
src/northbridge/amd/agesa/family10/reset_test.h → src/northbridge/amd/agesa/family15/reset_test.h
View File

29
src/southbridge/amd/sr5650/early_setup.c
View File

@ -49,13 +49,15 @@ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
}
/* family 10 only, for reg > 0xFF */
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \
IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)
static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
u32 val)
static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev,
u32 reg_pos, u32 mask, u32 val)
{
u32 reg_old, reg;
/* family 10 only, for reg > 0xFF */
if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10))
return;
reg = reg_old = pci_read_config32(fam10_dev, reg_pos);
reg &= ~mask;
reg |= val;
@ -63,10 +65,6 @@ static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 m
pci_write_config32(fam10_dev, reg_pos, reg);
}
}
#else
#define set_fam10_ext_cfg_enable_bits(a, b, c, d) do {} while (0)
#endif
/*
* Compliant with CIM_33's ATINB_PrepareInit
@ -222,8 +220,7 @@ void sr5650_htinit(void)
/* Enable Protocol checker */
set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \
IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
/* HT3 mode, RPR 5.4.3 */
set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);
@ -269,7 +266,7 @@ void sr5650_htinit(void)
//set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26);
/* HT Buffer Allocation for Ganged Links!!! */
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
}
}
@ -301,8 +298,6 @@ void sr5650_htinit_dect_and_enable_isochronous_link(void)
}
}
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \
IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)
void fam10_optimization(void)
{
device_t cpu_f0, cpu_f2, cpu_f3;
@ -310,6 +305,9 @@ void fam10_optimization(void)
msr_t msr;
u32 val;
if (!IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10))
return;
printk(BIOS_INFO, "fam10_optimization()\n");
msr = rdmsr(0xC001001F);
msr.hi |= 1 << 14; /* bit 46: EnableCf8ExtCfg */
@ -329,9 +327,6 @@ void fam10_optimization(void)
/* TODO: HT Buffer Allocation for (un)Ganged Links */
/* rpr Table 5-11, 5-12 */
}
#else
#define fam10_optimization() do {} while (0)
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
/*****************************************
* Compliant with CIM_33's ATINB_PCICFG_POR_TABLE