soc/intel/apollolake: Add CQOS config for CAR common code

Change-Id: I5947170a96e888cea2f3faac92355e72b63c1fef
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18735
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/Kconfig

@@ -275,6 +275,19 @@ config CAR_CQOS
 
 endchoice
 
+#
+# Each bit in QOS mask controls this many bytes. This is calculated as:
+# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
+#
+
+config CACHE_QOS_SIZE_PER_BIT
+	hex
+	default 0x20000 # 128 KB
+
+config L2_CACHE_SIZE
+	hex
+	default 0x100000
+
 config SPI_FLASH_INCLUDE_ALL_DRIVERS
 	bool
 	default n

src/soc/intel/apollolake/bootblock/cache_as_ram.S

@@ -142,7 +142,7 @@ clear_var_mtrr:
 #endif
 
 #if IS_ENABLED(CONFIG_CAR_CQOS)
-#if (CONFIG_DCACHE_RAM_SIZE == L2_CACHE_SIZE)
+#if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE)
 /*
  * If CAR size is set to full L2 size, mask is calculated as all-zeros.
  * This is not supported by the CPU/uCode.
@@ -152,7 +152,7 @@ clear_var_mtrr:
 	/* Calculate how many bits to be used for CAR */
 	xor	%edx, %edx
 	mov	$CONFIG_DCACHE_RAM_SIZE, %eax	/* dividend */
-	mov	$CACHE_QOS_SIZE_PER_BIT, %ecx	/* divisor */
+	mov	$CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx	/* divisor */
 	div	%ecx				/* result is in eax */
 	mov	%eax, %ecx			/* save to ecx */
 	mov	$1, %ebx

src/soc/intel/apollolake/include/soc/cpu.h

@@ -83,12 +83,6 @@ void enable_untrusted_mode(void);
 #define CACHE_BITS_PER_MASK		8
 #define CACHE_LINE_SIZE			64
 #define CACHE_SETS			1024
-/*
- * Each bit in QOS mask controls this many bytes. This is calculated as:
- * (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
- */
-#define CACHE_QOS_SIZE_PER_BIT		(128 * KiB)
-#define L2_CACHE_SIZE			0x100000
 
 #define BASE_CLOCK_MHZ		100