Changelog:
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Indrek Kruusa
Stefan Reinauer
parent
8ad7c06535
commit
8e3464109e
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@ -5,7 +5,6 @@
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#include <cpu/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#include <cpu/amd/lxdef.h>
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static void vsm_end_post_smi(void)
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{
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@ -19,37 +18,10 @@ static void vsm_end_post_smi(void)
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static void model_lx_init(device_t dev)
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{
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msr_t msr;
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printk_debug("model_lx_init\n");
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/* Turn on caching if we haven't already */
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/* Instruction Memory Configuration register
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* set EBE bit, required when L2 cache is enabled
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*/
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msr = rdmsr(CPU_IM_CONFIG);
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msr.lo |= 0x400;
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wrmsr(CPU_IM_CONFIG, msr);
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/* Data Memory Subsystem Configuration register
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* set EVCTONRPL bit, required when L2 cache is enabled in victim mode
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*/
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msr = rdmsr(CPU_DM_CONFIG0);
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msr.lo |= 0x4000;
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wrmsr(CPU_DM_CONFIG0, msr);
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/* invalidate L2 cache */
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msr.hi = 0x00;
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msr.lo = 0x10;
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wrmsr(L2_CONFIG_MSR, msr);
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/* Enable L2 cache */
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msr.hi = 0x00;
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msr.lo = 0x0f;
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wrmsr(L2_CONFIG_MSR, msr);
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x86_enable_cache();
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/* Enable the local cpu apics */
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@ -264,6 +264,10 @@
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#define RCONF_DMM_LOWER_RCNORM_SHIFT 0
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#define RCONF_DMM_LOWER_EN_SET (1<<8)
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/* ----- GX3 OK ---- */
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#define CPU_RCONF0 0x1810
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#define CPU_RCONF1 0x1811
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#define CPU_RCONF2 0x1812
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@ -272,10 +276,20 @@
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#define CPU_RCONF5 0x1815
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#define CPU_RCONF6 0x1816
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#define CPU_RCONF7 0x1817
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/* ------------------------ */
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/* ----- GX3 OK ---- */
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#define CPU_CR1_MSR 0x1881
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#define CPU_CR2_MSR 0x1882
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#define CPU_CR3_MSR 0x1883
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#define CPU_CR4_MSR 0x1884
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/* ------------------------ */
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/* ----- GX3 OK ---- */
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#define CPU_DC_INDEX 0x1890
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#define CPU_DC_DATA 0x1891
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#define CPU_DC_TAG 0x1892
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@ -285,6 +299,9 @@
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#define CPU_DTB_LRU 0x1899
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#define CPU_DTB_ENTRY 0x189A
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#define CPU_DTB_ENTRY_I 0x189B
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/* ------------------------ */
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#define CPU_L2TB_INDEX 0x189C
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#define CPU_L2TB_LRU 0x189D
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#define CPU_L2TB_ENTRY 0x189E
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@ -124,8 +124,8 @@ dir /pc80
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config chip.h
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chip northbridge/amd/lx
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register "irqmap" = "0xcab9"
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register "setupflash" = "0"
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register "irqmap" = "0xcba5"
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register "setupflash" = "1"
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device apic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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@ -138,20 +138,18 @@ chip northbridge/amd/lx
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register "enable_gpio0_inta" = "1"
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register "enable_ide_nand_flash" = "1"
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register "enable_uarta" = "1"
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register "audio_irq" = "5"
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register "usbf4_irq" = "10"
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register "usbf5_irq" = "10"
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register "usbf6_irq" = "0"
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register "usbf7_irq" = "0"
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register "audio_irq" = "11"
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register "usbf4_irq" = "5"
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register "usbf5_irq" = "5"
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register "usbf6_irq" = "5"
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register "usbf7_irq" = "5"
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device pci d.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
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register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
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register "unwanted_vpci[2]" = "0" # End of list has a zero
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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end
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end
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end
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@ -71,8 +71,9 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=2
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default HAVE_PIRQ_TABLE=0
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default IRQ_SLOT_COUNT=6
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#object irq_tables.o
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##
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@ -112,8 +113,8 @@ default CONFIG_ROM_STREAM = 1
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## The default compiler
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##
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default CROSS_COMPILE=""
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default CC="$(CROSS_COMPILE)gcc-3.4 -m32"
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default HOSTCC="gcc-3.4"
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## The Serial Console
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@ -7,24 +7,53 @@
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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#define ID_SLOT_PCI_NET 1 // ThinCan ethernet
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#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1
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#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2
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#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3
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#define ID_EMBED_PCI 0xff // onboard PCI device
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// CS5535 PCI INT[A-D] Interrupt Routing lines.
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#define NO_CONNECT 0 // not used
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#define CS_PCI_INTA 1 // PCI INTA
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#define CS_PCI_INTB 2 // PCI INTB
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#define CS_PCI_INTC 3 // PCI INTC
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#define CS_PCI_INTD 4 // PCI INTD
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// IRQ bitmap reference line FEDCBA9876543210
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// 0000110000100000b
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#define PCI_IRQ 0xc20 // PCI allowed IRQs here
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const struct irq_routing_table intel_irq_routing_table =
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{
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*2, /* there can be total 2 devices on the bus */
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32+16*6, /* there can be total 2 devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
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0x800, /* IRQs devoted exclusively to PCI usage */
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0x1078, /* Vendor */
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0x2, /* Device */
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0, /* Crap (miniport) */
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0x0800, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x208f, /* Device */
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0x00000000, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
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{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
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// Geode GX3 Host Bridge and VGA Graphics
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{0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
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// Realtek RTL8100/8139 Network Controller
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{0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
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// Reserved for future extensions
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{0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
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// Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
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{0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
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// Reserved for future extensions
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{0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
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// Reserved for future extensions
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{0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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@ -7,31 +7,33 @@
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#include "chip.h"
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static void init(struct device *dev) {
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/*
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static void init(struct device *dev)
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{
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unsigned bus = 0;
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unsigned devfn = PCI_DEVFN(0xf, 4);
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device_t usb = NULL;
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unsigned char usbirq = 0xa;
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*/
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unsigned devNic = PCI_DEVFN(0xd, 0);
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unsigned devUsb = PCI_DEVFN(0xf, 4);
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device_t usb = NULL, nic = NULL;
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unsigned char irqUsb = 0xa, irqNic = 0xb;
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printk_debug("ARTECGROUP DBE61 ENTER %s\n", __FUNCTION__);
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#if 0
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/* I can't think of any reason NOT to just set this. If it turns out we want this to be
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* conditional we can make it a config variable later.
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*/
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// FIXME: do we need to initialize USB OHCI this way?
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printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n",
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__FUNCTION__, bus, devUsb, irqUsb);
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// initialize the USB controller
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usb = dev_find_slot(bus, devUsb);
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if (!usb) printk_err("Could not find USB\n");
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else pci_write_config8(usb, PCI_INTERRUPT_LINE, irqUsb);
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printk_debug("%s (%x,%x) set NIC PCI interrupt line to %d\n",
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__FUNCTION__, bus, devNic, irqNic);
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// initialize the Realtek NIC
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nic = dev_find_slot(bus, devNic);
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if (!nic) printk_err("Could not find USB\n");
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else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic);
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printk_debug("%s (%x,%x)SET USB PCI interrupt line to %d\n",
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__FUNCTION__, bus, devfn, usbirq);
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usb = dev_find_slot(bus, devfn);
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if (! usb){
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printk_err("Could not find USB\n");
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} else {
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pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
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}
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#endif
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printk_debug("ARTECGROUP DBE61 EXIT %s\n", __FUNCTION__);
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}
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@ -9,6 +9,7 @@
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#include <bitops.h>
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#include "chip.h"
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#include "northbridge.h"
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#include <cpu/cpu.h>
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#include <cpu/amd/lxdef.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/cache.h>
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@ -274,6 +275,38 @@ static void enable_shadow(device_t dev)
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}
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static void enable_L2_cache(void) {
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msr_t msr;
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/* Instruction Memory Configuration register
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* set EBE bit, required when L2 cache is enabled
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*/
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msr = rdmsr(CPU_IM_CONFIG);
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msr.lo |= 0x400;
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wrmsr(CPU_IM_CONFIG, msr);
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/* Data Memory Subsystem Configuration register
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* set EVCTONRPL bit, required when L2 cache is enabled in victim mode
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*/
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msr = rdmsr(CPU_DM_CONFIG0);
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msr.lo |= 0x4000;
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wrmsr(CPU_DM_CONFIG0, msr);
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/* invalidate L2 cache */
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msr.hi = 0x00;
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msr.lo = 0x10;
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wrmsr(L2_CONFIG_MSR, msr);
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/* Enable L2 cache */
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msr.hi = 0x00;
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msr.lo = 0x0f;
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wrmsr(L2_CONFIG_MSR, msr);
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printk_debug("L2 cache enabled\n");
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}
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static void northbridge_init(device_t dev)
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{
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struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
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@ -456,8 +489,9 @@ static void enable_dev(struct device *dev)
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extern void cpubug(void);
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printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
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/* cpubug MUST be called before setup_lx(), so we force the issue here */
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enable_L2_cache();
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northbridgeinit();
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cpubug();
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/* cpubug(); GX3*/
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chipsetinit(nb);
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setup_lx();
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/* do this here for now -- this chip really breaks our device model */
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@ -1,13 +1,10 @@
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#include <cpu/amd/lxdef.h>
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#if 0
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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}
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#endif
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/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
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* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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@ -1,11 +1,11 @@
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# Config file for the olpc rev_a
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# Config file for the ThinCan dbe61
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target dbe61
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mainboard artecgroup/dbe61
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# leave 128k for vsa
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# leave 64k for vsa
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option CONFIG_COMPRESSED_ROM_STREAM=0
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option ROM_SIZE=1024*256-128*1024
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option ROM_SIZE=1024*256-64*1024
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option FALLBACK_SIZE=ROM_SIZE
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option DEFAULT_CONSOLE_LOGLEVEL = 11
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