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mb/system76/tgl-h: Convert oryp8 to a variant 

Change-Id: Ied55add6d7549f165d8b97032d7f21ede0ce2dde
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
This commit is contained in:
Tim Crawford 2022-09-29 12:11:34 -06:00 committed by Felix Held
parent def33cc5bb
commit 8e3787eaf0
28 changed files with 48 additions and 408 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
src/mainboard/system76/oryp8/Kconfig
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@ -1,64 +0,0 @@
if BOARD_SYSTEM76_ORYP8
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_HID
select DRIVERS_I2C_TAS5825M
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MEMORY_MAPPED_TPM
select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
select PCIEXP_HOTPLUG
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
select SOC_INTEL_TIGERLAKE
select SOC_INTEL_TIGERLAKE_PCH_H
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
select TPM_MEASURED_BOOT
select TPM_RDRESP_NEED_DELAY
config MAINBOARD_DIR
default "system76/oryp8"
config MAINBOARD_PART_NUMBER
default "oryp8"
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Oryx Pro"
config MAINBOARD_VERSION
default "oryp8"
config CBFS_SIZE
default 0xA00000
config CONSOLE_POST
default y
config DIMM_MAX
default 4
config ONBOARD_VGA_IS_PRIMARY
default y
config POST_DEVICE
default n
config UART_FOR_CONSOLE
default 2
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

2
src/mainboard/system76/oryp8/Kconfig.name
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@ -1,2 +0,0 @@
config BOARD_SYSTEM76_ORYP8
bool "oryp8"

13
src/mainboard/system76/oryp8/Makefile.inc
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@ -1,13 +0,0 @@
## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c
bootblock-y += gpio_early.c
romstage-y += romstage.c
ramstage-y += gpio.c
ramstage-y += hda_verb.c
ramstage-y += ramstage.c
ramstage-y += tas5825m.c

9
src/mainboard/system76/oryp8/acpi/mainboard.asl
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@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
}

46
src/mainboard/system76/oryp8/acpi/sleep.asl
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@ -1,46 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/gpio.h>
Method (PGPM, 1, Serialized)
{
For (Local0 = 0, Local0 < 6, Local0++)
{
\_SB.PCI0.CGPM (Local0, Arg0)
}
}
/*
* Method called from _PTS prior to system sleep state entry
* Enables dynamic clock gating for all 5 GPIO communities
*/
Method (MPTS, 1, Serialized)
{
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
}
/*
* Method called from _WAK prior to system sleep state wakeup
* Disables dynamic clock gating for all 5 GPIO communities
*/
Method (MWAK, 1, Serialized)
{
PGPM (0)
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
}
/*
* S0ix Entry/Exit Notifications
* Called from \_SB.PEPD._DSM
*/
Method (MS0X, 1, Serialized)
{
If (Arg0 == 1) {
/* S0ix Entry */
PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
} Else {
/* S0ix Exit */
PGPM (0)
}
}

8
src/mainboard/system76/oryp8/board_info.txt
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@ -1,8 +0,0 @@
Vendor name: System76
Board name: oryp8
Category: laptop
Release year: 2021
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

9
src/mainboard/system76/oryp8/bootblock.c
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@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <mainboard/gpio.h>
void bootblock_mainboard_init(void)
{
mainboard_configure_early_gpios();
}

3
src/mainboard/system76/oryp8/cmos.default
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@ -1,3 +0,0 @@
boot_option=Fallback
debug_level=Debug
me_state=Disable

39
src/mainboard/system76/oryp8/cmos.layout
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@ -1,39 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
entries
0 384 r 0 reserved_memory
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# RTC_CLK_ALTCENTURY
400 8 r 0 century
412 4 e 6 debug_level
416 1 e 2 me_state
417 3 h 0 me_state_counter
984 16 h 0 check_sum
enumerations
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 408 983 984

34
src/mainboard/system76/oryp8/dsdt.asl
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@ -1,34 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
#include <soc/intel/tigerlake/acpi/tcss.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/pc/ps2_controller.asl>
}
#include "acpi/mainboard.asl"
}

9
src/mainboard/system76/oryp8/include/mainboard/gpio.h
View File

@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
void mainboard_configure_early_gpios(void);
void mainboard_configure_gpios(void);
#endif

30
src/mainboard/system76/oryp8/romstage.c
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@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <fsp/util.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
static const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
.ddr4_config = {
.dq_pins_interleaved = true,
},
};
static const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const bool half_populated = false;
// Enable M.2 PCIE 4.0 and PEG1
mupd->FspmConfig.CpuPcieRpEnableMask = 0x3;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}

9
src/mainboard/system76/tgl-h/Kconfig
View File

@ -1,9 +1,10 @@
if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060_B
if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060_B || BOARD_SYSTEM76_ORYP8
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_HID
select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP8
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
@ -17,6 +18,8 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_TPM2
select MAINBOARD_USES_IFD_GBE_REGION if BOARD_SYSTEM76_GAZE16_3060_B
select NO_UART_ON_SUPERIO
select PCIEXP_HOTPLUG if BOARD_SYSTEM76_ORYP8
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G if BOARD_SYSTEM76_ORYP8
select SOC_INTEL_TIGERLAKE
select SOC_INTEL_TIGERLAKE_PCH_H
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
@ -32,18 +35,22 @@ config MAINBOARD_PART_NUMBER
default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060
default "gaze16-3060-b" if BOARD_SYSTEM76_GAZE16_3060_B
default "oryp8" if BOARD_SYSTEM76_ORYP8
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Oryx Pro" if BOARD_SYSTEM76_ORYP8
default "Gazelle"
config MAINBOARD_VERSION
default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060
default "gaze16-3060-b" if BOARD_SYSTEM76_GAZE16_3060_B
default "oryp8" if BOARD_SYSTEM76_ORYP8
config VARIANT_DIR
default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060_B
default "oryp8" if BOARD_SYSTEM76_ORYP8
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"

3
src/mainboard/system76/tgl-h/Kconfig.name
View File

@ -6,3 +6,6 @@ config BOARD_SYSTEM76_GAZE16_3060
config BOARD_SYSTEM76_GAZE16_3060_B
bool "gaze16 3060-b"
config BOARD_SYSTEM76_ORYP8
bool "oryp8"

1
src/mainboard/system76/tgl-h/Makefile.inc
View File

@ -11,3 +11,4 @@ ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c

13
src/mainboard/system76/tgl-h/devicetree.cb
View File

@ -91,11 +91,6 @@ chip soc/intel/tigerlake
register "DdiPortAHpd" = "1"
register "DdiPortADdc" = "0"
# DDIB is HDMI
register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref dptf on end
@ -124,6 +119,14 @@ chip soc/intel/tigerlake
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""SYNA1202""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_R12)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end
device ref heci1 on end
device ref uart2 on

1
src/mainboard/system76/tgl-h/dsdt.asl
View File

@ -19,6 +19,7 @@ DefinitionBlock(
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
#include <soc/intel/tigerlake/acpi/tcss.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

6
src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
View File

@ -17,6 +17,12 @@ chip soc/intel/tigerlake
device generic 0 on end
end
end
device ref igpu on
# DDIB is HDMI
register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
end
device ref peg0 on
# PCIe PEG0 x4, Clock 4 (SSD2)
register "PcieClkSrcUsage[4]" = "0x40"

6
src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
View File

@ -17,6 +17,12 @@ chip soc/intel/tigerlake
device generic 0 on end
end
end
device ref igpu on
# DDIB is HDMI
register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
end
device ref peg0 on
# PCIe PEG0 x4, Clock 7 (SSD1)
register "PcieClkSrcUsage[7]" = "0x40"

2
src/mainboard/system76/tgl-h/variants/oryp8/board_info.txt Normal file
View File

@ -0,0 +1,2 @@
Board name: oryp8
Release year: 2021

0
src/mainboard/system76/oryp8/data.vbt → src/mainboard/system76/tgl-h/variants/oryp8/data.vbt
View File

4
src/mainboard/system76/oryp8/gpio.c → src/mainboard/system76/tgl-h/variants/oryp8/gpio.c
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
#include <variant/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
@ -275,7 +275,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DATA0
};
void mainboard_configure_gpios(void)
void variant_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

4
src/mainboard/system76/oryp8/gpio_early.c → src/mainboard/system76/tgl-h/variants/oryp8/gpio_early.c
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
#include <variant/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
@ -11,7 +11,7 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
};
void mainboard_configure_early_gpios(void)
void variant_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

0
src/mainboard/system76/oryp8/hda_verb.c → src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c
View File

123
src/mainboard/system76/oryp8/devicetree.cb → src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
View File

@ -1,18 +1,4 @@
chip soc/intel/tigerlake
register "common_soc_config" = "{
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
}"
# ACPI (soc/intel/tigerlake/acpi.c)
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
# CPU (soc/intel/tigerlake/cpu.c)
# Power limits
register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
.tdp_pl1_override = 45,
@ -23,71 +9,12 @@ chip soc/intel/tigerlake
.tdp_pl2_override = 90,
}"
# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
# Enable C6 DRAM
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate" = "SLEW_FAST_8"
register "FastPkgCRampDisable" = "1"
# FIVR configuration
# Read EXT_RAIL_CONFIG to determine bitmaps
# sudo devmem2 0xfe0011b8
# 0x0
# Read EXT_V1P05_VR_CONFIG
# sudo devmem2 0xfe0011c0
# 0x1a42000
# Read EXT_VNN_VR_CONFIG0
# sudo devmem2 0xfe0011c4
# 0x1a42000
# TODO: v1p05 voltage and vnn icc max?
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = 0,
.vnn_enable_bitmap = 0,
.v1p05_supported_voltage_bitmap = 0,
.vnn_supported_voltage_bitmap = 0,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1050,
}"
# Read LPM_EN, make sure to invert the bits
# sudo devmem2 0xfe001c78
# 0x9
register "LpmStateDisableMask" = "
LPM_S0i2_1 |
LPM_S0i2_2 |
LPM_S0i3_1 |
LPM_S0i3_2 |
LPM_S0i3_3 |
LPM_S0i3_4
"
# Thermal
register "tcc_offset" = "10"
# Enable CNVi BT
register "CnviBtCore" = "true"
# PM Util (soc/intel/tigerlake/pmutil.c)
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_R"
register "pmc_gpe0_dw1" = "PMC_GPP_B"
register "pmc_gpe0_dw2" = "PMC_GPP_D"
# Actual device tree
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
subsystemid 0x1558 0x65f1 inherit
#From CPU EDS(575683)
device ref system_agent on end
device ref peg1 on
# PCIe PEG1 x16, Clock 9 (DGPU)
register "PcieClkSrcUsage[9]" = "0x41"
@ -103,28 +30,16 @@ chip soc/intel/tigerlake
device generic 0 on end
end
end
device ref igpu on
# DDIA is eDP
register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
register "DdiPortAHpd" = "1"
register "DdiPortADdc" = "0"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref dptf on end
device ref peg0 on
# PCIe PEG0 x4, Clock 7 (SSD1)
register "PcieClkSrcUsage[7]" = "0x40"
register "PcieClkSrcClkReq[7]" = "7"
end
device ref tbt_pcie_rp0 on end # TYPEC1
device ref gna on end
device ref north_xhci on # TYPEC1
register "TcssXhciEn" = "1"
end
device ref tbt_dma0 on end # TYPEC1
# From PCH EDS(615985)
device ref south_xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
@ -140,30 +55,6 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
end
device ref shared_ram on end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c0 on
# Touchpad I2C bus
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""SYNA1202""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_R12)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end
device ref heci1 on end
device ref uart2 on
# Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
end
device ref sata on
register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
end
@ -197,25 +88,11 @@ chip soc/intel/tigerlake
register "PcieClkSrcClkReq[6]" = "6"
register "PcieRpSlotImplemented[8]" = "1"
end
device ref pch_espi on
register "gen1_dec" = "0x00040069" # EC PM channel
register "gen2_dec" = "0x00fc0E01" # AP/EC command
register "gen3_dec" = "0x00fc0F01" # AP/EC debug
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref p2sb on end
device ref pmc hidden end
device ref hda on
register "PchHdaAudioLinkHdaEnable" = "1"
end
device ref smbus on
chip drivers/i2c/tas5825m
register "id" = "0"
device i2c 4e on end # (8bit address: 0x9c)
end
end
device ref fast_spi on end
end
end

9
src/mainboard/system76/oryp8/ramstage.c → src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c
View File

@ -1,13 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/ramstage.h>
#include <smbios.h>
smbios_wakeup_type smbios_system_wakeup_type(void)
{
return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
}
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
@ -28,6 +21,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
// Low latency legacy I/O
params->PchLegacyIoLowLatency = 1;
mainboard_configure_gpios();
}

9
src/mainboard/system76/tgl-h/variants/oryp8/romstage.c Normal file
View File

@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <variant/romstage.h>
void variant_memory_init_params(FSPM_UPD *mupd)
{
// Enable M.2 PCIE 4.0 and PEG1
mupd->FspmConfig.CpuPcieRpEnableMask = 0x3;
}

0
src/mainboard/system76/oryp8/tas5825m.c → src/mainboard/system76/tgl-h/variants/oryp8/tas5825m.c
View File