diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 1ef929c77c..dd21143798 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -67,7 +67,7 @@ void fast_spi_init(void)
 }
 
 /*
- * Set FAST_SPIBAR BIOS Control BILD bit.
+ * Set FAST_SPIBAR BIOS Control register based on input bit field.
  */
 static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit)
 {
@@ -80,12 +80,22 @@ static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit)
 	pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bc_cntl);
 }
 
+/*
+ * Ensure an additional read back after performing lock down
+ */
+static void fast_spi_read_post_write(uint8_t reg)
+{
+	pci_read_config8(PCH_DEV_SPI, reg);
+}
+
 /*
  * Set FAST_SPIBAR BIOS Control BILD bit.
  */
 void fast_spi_set_bios_interface_lock_down(void)
 {
 	fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_BILD);
+
+	fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
 }
 
 /*
@@ -94,6 +104,9 @@ void fast_spi_set_bios_interface_lock_down(void)
 void fast_spi_set_lock_enable(void)
 {
 	fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_LOCK_ENABLE);
+
+
+	fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
 }
 
 /*
@@ -102,6 +115,8 @@ void fast_spi_set_lock_enable(void)
 void fast_spi_set_eiss(void)
 {
 	fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EISS);
+
+	fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
 }
 
 /*