mb/hp: Add CMOS support for all HP Elitebook models
The cmos.layout files are copied from lenovo/x230 with EC options removed. It's tested on 8470p and the power_on_after_fail option works. Change-Id: I0a50a25798fd31b7acccf9872c50dac2718ce895 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/22842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Iru Cai
Arthur Heymans
parent
d46a3502b6
commit
8e4384d0b4
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@ -31,6 +31,8 @@ config BOARD_SPECIFIC_OPTIONS
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select EC_HP_KBC1126
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select MAINBOARD_HAS_LIBGFXINIT
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select GFX_GMA_INTERNAL_IS_LVDS
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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config HAVE_IFD_BIN
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bool
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@ -0,0 +1,6 @@
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boot_option=Fallback
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debug_level=Spew
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power_on_after_fail=Disable
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nmi=Enable
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volume=0x3
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sata_mode=AHCI
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@ -0,0 +1,116 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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#400 8 r 0 reserved for century byte
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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421 1 e 9 sata_mode
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# coreboot config options: cpu
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#424 8 r 0 unused
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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#435 5 r 0 unused
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440 8 h 0 volume
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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960 16 r 0 mrc_scrambler_seed_chk
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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9 0 AHCI
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9 1 Compatible
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11 0 32M
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11 1 64M
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11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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11 6 224M
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# -----------------------------------------------------------------
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checksums
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checksum 392 447 984
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@ -31,6 +31,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select EC_HP_KBC1126
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select MAINBOARD_HAS_LIBGFXINIT
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select GFX_GMA_INTERNAL_IS_LVDS
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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config HAVE_IFD_BIN
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bool
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@ -0,0 +1,6 @@
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boot_option=Fallback
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debug_level=Spew
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power_on_after_fail=Disable
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nmi=Enable
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volume=0x3
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sata_mode=AHCI
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@ -0,0 +1,116 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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#400 8 r 0 reserved for century byte
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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421 1 e 9 sata_mode
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# coreboot config options: cpu
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#424 8 r 0 unused
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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#435 5 r 0 unused
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440 8 h 0 volume
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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960 16 r 0 mrc_scrambler_seed_chk
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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9 0 AHCI
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9 1 Compatible
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11 0 32M
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11 1 64M
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11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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11 6 224M
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# -----------------------------------------------------------------
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checksums
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checksum 392 447 984
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@ -33,6 +33,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select GFX_GMA_INTERNAL_IS_LVDS
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select EC_HP_KBC1126
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select SUPERIO_SMSC_LPC47N217
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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config HAVE_IFD_BIN
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bool
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@ -0,0 +1,6 @@
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boot_option=Fallback
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debug_level=Spew
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power_on_after_fail=Disable
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nmi=Enable
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volume=0x3
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sata_mode=AHCI
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@ -0,0 +1,116 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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#400 8 r 0 reserved for century byte
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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421 1 e 9 sata_mode
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# coreboot config options: cpu
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#424 8 r 0 unused
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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#435 5 r 0 unused
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440 8 h 0 volume
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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960 16 r 0 mrc_scrambler_seed_chk
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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9 0 AHCI
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9 1 Compatible
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11 0 32M
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11 1 64M
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11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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11 6 224M
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# -----------------------------------------------------------------
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checksums
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checksum 392 447 984
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@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select GFX_GMA_INTERNAL_IS_LVDS
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select EC_HP_KBC1126
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select SUPERIO_SMSC_LPC47N217
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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config HAVE_IFD_BIN
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bool
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@ -0,0 +1,6 @@
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boot_option=Fallback
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debug_level=Spew
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power_on_after_fail=Disable
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nmi=Enable
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volume=0x3
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sata_mode=AHCI
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@ -0,0 +1,116 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
|
||||
##
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||||
## This program is free software; you can redistribute it and/or modify
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||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
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||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
## GNU General Public License for more details.
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||||
##
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||||
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||||
# -----------------------------------------------------------------
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||||
entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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||||
384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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||||
#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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||||
|
||||
#400 8 r 0 reserved for century byte
|
||||
|
||||
# coreboot config options: southbridge
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||||
408 1 e 1 nmi
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||||
409 2 e 7 power_on_after_fail
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||||
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421 1 e 9 sata_mode
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# coreboot config options: cpu
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#424 8 r 0 unused
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# coreboot config options: northbridge
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||||
432 3 e 11 gfx_uma_size
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#435 5 r 0 unused
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||||
|
||||
440 8 h 0 volume
|
||||
|
||||
# SandyBridge MRC Scrambler Seed values
|
||||
896 32 r 0 mrc_scrambler_seed
|
||||
928 32 r 0 mrc_scrambler_seed_s3
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||||
960 16 r 0 mrc_scrambler_seed_chk
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||||
|
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# coreboot config options: check sums
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||||
984 16 h 0 check_sum
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||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
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||||
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||||
#ID value text
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||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
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2 1 Disable
|
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4 0 Fallback
|
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4 1 Normal
|
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6 1 Emergency
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6 2 Alert
|
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6 3 Critical
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6 4 Error
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6 5 Warning
|
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6 6 Notice
|
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6 7 Info
|
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6 8 Debug
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6 9 Spew
|
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7 0 Disable
|
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7 1 Enable
|
||||
7 2 Keep
|
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9 0 AHCI
|
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9 1 Compatible
|
||||
11 0 32M
|
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11 1 64M
|
||||
11 2 96M
|
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11 3 128M
|
||||
11 4 160M
|
||||
11 5 192M
|
||||
11 6 224M
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 447 984
|
||||
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