soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC
Below changes are implemented: 1. Move HFSTS1 register definition to SoC since HFSTS1 register definition is specific to a SoC. Moving structure back to SoC specific to avoid unnecessay SoC specific macros in the common code. 2. Define a set of APIs in common code since CSE operation modes and working states are same across SoCs. cse_is_hfs1_com_normal(void) cse_is_hfs1_com_secover_mei_msg(void) cse_is_hfs1_com_soft_temp_disable(void) cse_is_hfs1_cws_normal(void) 3. Modify existing code to use callbacks to get data of me_hfs1 structure. TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -0,0 +1,43 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _APOLLOLAKE_ME_H_
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#define _APOLLOLAKE_ME_H_
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/* ME Host Firmware Status register 1 */
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union me_hfsts1 {
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u32 data;
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struct {
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u32 working_state: 4;
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u32 mfg_mode: 1;
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u32 fpt_bad: 1;
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u32 operation_state: 3;
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u32 fw_init_complete: 1;
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u32 ft_bup_ld_flr: 1;
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u32 update_in_progress: 1;
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u32 error_code: 4;
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u32 operation_mode: 4;
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u32 reset_count: 4;
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u32 boot_options_present: 1;
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u32 bist_finished: 1;
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u32 hw_bist_passed: 1;
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u32 bist_reset_request: 1;
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u32 current_power_source: 2;
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u32 reserved: 1;
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u32 d0i3_support_valid: 1;
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} __packed fields;
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};
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#endif /* _APOLLOLAKE_ME_H_ */
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@ -16,6 +16,34 @@
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#ifndef _CANNONLAKE_ME_H_
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#define _CANNONLAKE_ME_H_
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/* ME Host Firmware Status register 1 */
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union me_hfsts1 {
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u32 data;
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struct {
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u32 working_state: 4;
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u32 mfg_mode: 1;
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u32 fpt_bad: 1;
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u32 operation_state: 3;
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u32 fw_init_complete: 1;
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u32 ft_bup_ld_flr: 1;
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u32 update_in_progress: 1;
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u32 error_code: 4;
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u32 operation_mode: 4;
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u32 reset_count: 4;
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u32 boot_options_present: 1;
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#if CONFIG(SOC_INTEL_COMETLAKE)
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u32 invoke_enhance_dbg_mode:1;
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#else
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u32 reserved0: 1;
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#endif
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u32 bist_test_state: 1;
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u32 bist_reset_request: 1;
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u32 current_power_source: 2;
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u32 reserved1: 1;
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u32 d0i3_support_valid: 1;
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} __packed fields;
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};
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void dump_me_status(void *unused);
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#endif /* _CANNONLAKE_ME_H_ */
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@ -24,6 +24,7 @@
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#include <intelblocks/cse.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/me.h>
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#include <string.h>
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#include <timer.h>
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@ -238,17 +239,35 @@ static int cse_ready(void)
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return csr & CSR_READY;
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}
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/*
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* Checks if CSE is in ME_HFS1_COM_SECOVER_MEI_MSG operation mode. This is the mode where
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* CSE will allow reflashing of CSE region.
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*/
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static uint8_t check_cse_sec_override_mode(void)
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static bool cse_check_hfs1_com(int mode)
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{
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union me_hfsts1 hfs1;
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hfs1.data = me_read_config32(PCI_ME_HFSTS1);
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if (hfs1.fields.operation_mode == ME_HFS1_COM_SECOVER_MEI_MSG)
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return 1;
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return 0;
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return hfs1.fields.operation_mode == mode;
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}
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bool cse_is_hfs1_cws_normal(void)
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{
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union me_hfsts1 hfs1;
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hfs1.data = me_read_config32(PCI_ME_HFSTS1);
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if (hfs1.fields.working_state == ME_HFS1_CWS_NORMAL)
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return true;
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return false;
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}
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bool cse_is_hfs1_com_normal(void)
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{
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return cse_check_hfs1_com(ME_HFS1_COM_NORMAL);
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}
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bool cse_is_hfs1_com_secover_mei_msg(void)
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{
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return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG);
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}
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bool cse_is_hfs1_com_soft_temp_disable(void)
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{
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return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE);
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}
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/* Makes the host ready to communicate with CSE */
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@ -266,7 +285,7 @@ uint8_t wait_cse_sec_override_mode(void)
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{
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY);
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while (!check_cse_sec_override_mode()) {
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while (!cse_is_hfs1_com_secover_mei_msg()) {
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udelay(HECI_DELAY);
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if (stopwatch_expired(&sw))
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return 0;
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@ -632,18 +651,15 @@ int send_hmrfpo_enable_msg(void)
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struct hmrfpo_enable_resp resp;
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size_t resp_size = sizeof(struct hmrfpo_enable_resp);
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union me_hfsts1 hfs1;
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printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n");
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hfs1.data = me_read_config32(PCI_ME_HFSTS1);
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/*
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* This command can be run only if:
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* - Working state is normal and
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* - Operation mode is normal or temporary disable mode.
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*/
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if (hfs1.fields.working_state != ME_HFS1_CWS_NORMAL ||
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(hfs1.fields.operation_mode != ME_HFS1_COM_NORMAL &&
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hfs1.fields.operation_mode != ME_HFS1_COM_SOFT_TEMP_DISABLE)) {
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if (!cse_is_hfs1_cws_normal() ||
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(!cse_is_hfs1_com_normal() && !cse_is_hfs1_com_soft_temp_disable())) {
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printk(BIOS_ERR, "HECI: ME not in required Mode\n");
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goto failed;
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}
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@ -51,30 +51,6 @@ enum {
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PCI_ME_HFSTS6 = 0x6C,
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};
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/* ME Host Firmware Status register 1 */
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union me_hfsts1 {
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u32 data;
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struct {
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u32 working_state: 4;
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u32 mfg_mode: 1;
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u32 fpt_bad: 1;
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u32 operation_state: 3;
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u32 fw_init_complete: 1;
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u32 ft_bup_ld_flr: 1;
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u32 update_in_progress: 1;
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u32 error_code: 4;
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u32 operation_mode: 4;
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u32 reset_count: 4;
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u32 boot_options_present: 1;
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u32 reserved1: 1;
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u32 bist_test_state: 1;
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u32 bist_reset_request: 1;
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u32 current_power_source: 2;
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u32 d3_support_valid: 1;
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u32 d0i3_support_valid: 1;
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} __packed fields;
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};
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/* HECI Message Header */
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struct mkhi_hdr {
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uint8_t group_id;
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#define MKHI_HMRFPO_LOCKED 1
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#define MKHI_HMRFPO_ENABLED 2
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/*
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* Checks current working operation state is normal or not.
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* Returns true if CSE's current working state is normal, otherwise false.
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*/
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bool cse_is_hfs1_cws_normal(void);
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/*
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* Checks CSE's current operation mode is normal or not.
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* Returns true if CSE's current operation mode is normal, otherwise false.
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*/
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bool cse_is_hfs1_com_normal(void);
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/*
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* Checks CSE's current operation mode is SECOVER_MEI_MSG or not.
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* Returns true if CSE's current operation mode is SECOVER_MEI_MSG, otherwise false.
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*/
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bool cse_is_hfs1_com_secover_mei_msg(void);
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/*
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* Checks CSE's current operation mode is Soft Disable Mode or not.
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* Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false.
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*/
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bool cse_is_hfs1_com_soft_temp_disable(void);
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#endif // SOC_INTEL_COMMON_CSE_H
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@ -0,0 +1,43 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ICELAKE_ME_H_
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#define _ICELAKE_ME_H_
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/* ME Host Firmware Status register 1 */
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union me_hfsts1 {
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u32 data;
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struct {
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u32 working_state: 4;
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u32 mfg_mode: 1;
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u32 fpt_bad: 1;
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u32 operation_state: 3;
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u32 fw_init_complete: 1;
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u32 ft_bup_ld_flr: 1;
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u32 update_in_progress: 1;
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u32 error_code: 4;
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u32 operation_mode: 4;
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u32 reset_count: 4;
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u32 boot_options_present: 1;
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u32 reserved1: 1;
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u32 bist_test_state: 1;
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u32 bist_reset_request: 1;
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u32 current_power_source: 2;
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u32 reserved: 1;
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u32 d0i3_support_valid: 1;
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} __packed fields;
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};
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#endif /* _ICELAKE_ME_H_ */
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#define ME_HFS2_PMEVENT_CM3_CM3PG 0xe
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#define ME_HFS2_PMEVENT_CM0PG_CM0 0xf
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/* ME Host Firmware Status register 1 */
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union me_hfsts1 {
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u32 data;
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struct {
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u32 working_state: 4;
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u32 mfg_mode: 1;
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u32 fpt_bad: 1;
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u32 operation_state: 3;
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u32 fw_init_complete: 1;
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u32 ft_bup_ld_flr: 1;
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u32 update_in_progress: 1;
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u32 error_code: 4;
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u32 operation_mode: 4;
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u32 reset_count: 4;
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u32 boot_options_present: 1;
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u32 reserved1: 1;
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u32 bist_test_state: 1;
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u32 bist_reset_request: 1;
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u32 current_power_source: 2;
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u32 d3_support_valid: 1;
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u32 d0i3_support_valid: 1;
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} __packed fields;
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};
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union me_hfs2 {
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u32 data;
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struct {
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@ -0,0 +1,43 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _TIGERLAKE_ME_H_
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#define _TIGERLAKE_ME_H_
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/* ME Host Firmware Status register 1 */
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union me_hfsts1 {
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u32 data;
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struct {
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u32 working_state: 4;
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u32 spi_protection_mode: 1;
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u32 fpt_bad: 1;
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u32 operation_state: 3;
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u32 fw_init_complete: 1;
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u32 ft_bup_ld_flr: 1;
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u32 update_in_progress: 1;
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u32 error_code: 4;
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u32 operation_mode: 4;
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u32 reset_count: 4;
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u32 boot_options_present: 1;
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u32 invoke_enhance_dbg_mode: 1;
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u32 bist_test_state: 1;
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u32 bist_reset_request: 1;
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u32 current_power_source: 2;
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u32 reserved: 1;
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u32 d0i3_support_valid: 1;
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} __packed fields;
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};
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#endif /* _TIGERLAKE_ME_H_ */
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