mb/pcengines/apu2: enable PCIe power management features
Enable ASPM L0s and L1, Common Clock and Clock Power Management for all PCIe ports. TEST=boot Debian linux and check new PCIe capabilities appear in lspci Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0a4c83731742f31ab8ef1d326e800dfdc2abb1b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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c04871a398
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8e46d42009
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@ -30,6 +30,10 @@ config BOARD_SPECIFIC_OPTIONS
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select GENERIC_SPD_BIN
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select GENERIC_SPD_BIN
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_LPC_TPM
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select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
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select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_L1_SUB_STATE
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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string
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string
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@ -33,7 +33,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
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HotplugDisabled,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, PCIE_PORT3_RESET_ID, 0)
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AspmL0sL1,
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PCIE_PORT3_RESET_ID,
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ClkPmSupportEnabled)
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},
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},
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/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
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/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
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{
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{
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@ -43,7 +45,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
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HotplugDisabled,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, PCIE_NIC_RESET_ID, 0)
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AspmL0sL1,
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PCIE_NIC_RESET_ID,
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ClkPmSupportEnabled)
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},
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},
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/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
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/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
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{
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{
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@ -53,7 +57,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
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HotplugDisabled,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, PCIE_NIC_RESET_ID, 0)
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AspmL0sL1,
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PCIE_NIC_RESET_ID,
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ClkPmSupportEnabled)
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},
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},
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/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
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/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
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{
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{
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@ -63,7 +69,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
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HotplugDisabled,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, PCIE_NIC_RESET_ID, 0)
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AspmL0sL1,
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PCIE_NIC_RESET_ID,
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ClkPmSupportEnabled)
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},
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},
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/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
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/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
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{
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{
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@ -73,7 +81,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
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HotplugDisabled,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, PCIE_GFX_RESET_ID, 0)
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AspmL0sL1,
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PCIE_GFX_RESET_ID,
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ClkPmSupportEnabled)
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}
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}
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};
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};
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