GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/pcengines/apu2: enable PCIe power management features 

Enable ASPM L0s and L1, Common Clock and Clock Power Management for
all PCIe ports.

TEST=boot Debian linux and check new PCIe capabilities appear in lspci

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I0a4c83731742f31ab8ef1d326e800dfdc2abb1b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Michał Żygowski 2020-03-20 16:19:55 +01:00
parent c04871a398
commit 8e46d42009
2 changed files with 19 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/pcengines/apu2/Kconfig
View File

@ -30,6 +30,10 @@ config BOARD_SPECIFIC_OPTIONS
select GENERIC_SPD_BIN select GENERIC_SPD_BIN
select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_LPC_TPM
select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
select PCIEXP_ASPM
select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK
select PCIEXP_L1_SUB_STATE
config MAINBOARD_DIR config MAINBOARD_DIR
string string

20
src/mainboard/pcengines/apu2/OemCustomize.c
View File

@ -33,7 +33,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
AspmDisabled, PCIE_PORT3_RESET_ID, 0) AspmL0sL1,
PCIE_PORT3_RESET_ID,
ClkPmSupportEnabled)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{ {
@ -43,7 +45,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
AspmDisabled, PCIE_NIC_RESET_ID, 0) AspmL0sL1,
PCIE_NIC_RESET_ID,
ClkPmSupportEnabled)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{ {
@ -53,7 +57,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
AspmDisabled, PCIE_NIC_RESET_ID, 0) AspmL0sL1,
PCIE_NIC_RESET_ID,
ClkPmSupportEnabled)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{ {
@ -63,7 +69,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
AspmDisabled, PCIE_NIC_RESET_ID, 0) AspmL0sL1,
PCIE_NIC_RESET_ID,
ClkPmSupportEnabled)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{ {
@ -73,7 +81,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
AspmDisabled, PCIE_GFX_RESET_ID, 0) AspmL0sL1,
PCIE_GFX_RESET_ID,
ClkPmSupportEnabled)
} }
}; };