mb/intel/jasperlake_rvp: Update Power Limit2 minimum value

Update Power Limit2 (PL2) minimum value to the same as maximum value for
jasperlake rvp board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.

BUG=None
BRANCH=None
TEST=Build and test on jasperlake rvp board

Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Sumeet R Pawnikar 2020-11-04 10:23:15 +05:30 committed by Patrick Georgi
parent ac12976f0c
commit 8e57299a0d
1 changed files with 1 additions and 1 deletions

View File

@ -189,7 +189,7 @@ chip soc/intel/jasperlake
.time_window_max = 1 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 6000,
.min_power = 20000,
.max_power = 20000,
.time_window_min = 1 * MSECS_PER_SEC,
.time_window_max = 1 * MSECS_PER_SEC,