arch/riscv: Refactor bootblock.S
A few things are currently missing: - The trap handler doesn't set the stack pointer, which can easily result in trap loops or memory corruptions. - The SBI trampolin page (as described in version 1.9 of the RISC-V Privileged Architecture Specification), has been removed for now. Change-Id: Id89c859fab354501c94a0e82d349349c29fa4cc6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15591 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan Neuschäfer
Ronald G. Minnich
parent
62bd9f93dd
commit
8e63017096
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@ -28,6 +28,9 @@ endif
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################################################################################
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################################################################################
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
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bootblock-y += id.S
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$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
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bootblock-y = bootblock.S stages.c
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bootblock-y = bootblock.S stages.c
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bootblock-y += trap_util.S
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bootblock-y += trap_util.S
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bootblock-y += trap_handler.c
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bootblock-y += trap_handler.c
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@ -1,7 +1,8 @@
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/*
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/*
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* Early initialization code for aarch64 (a.k.a. armv8)
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* Early initialization code for RISC-V
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*
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*
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* Copyright 2013 Google Inc.
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* Copyright 2013 Google Inc.
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* Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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*
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*
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* This program is free software; you can redistribute it and/or
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* modify it under the terms of the GNU General Public License as
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@ -13,7 +14,7 @@
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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// See LICENSE for license details. relating to the _start code in this file.
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#include <arch/encoding.h>
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#include <arch/encoding.h>
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.section ".text._start", "ax", %progbits
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.section ".text._start", "ax", %progbits
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@ -24,130 +25,24 @@ _start:
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#define STACK_START 0x80800000 /* 2GiB + 8MiB */
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#define STACK_START 0x80800000 /* 2GiB + 8MiB */
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#define STACK_SIZE 0x0000fff0
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#define STACK_SIZE 0x0000fff0
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// pending figuring out this f-ing toolchain. Hardcode what we know works.
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li sp, STACK_START + STACK_SIZE
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li sp, STACK_START + STACK_SIZE
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# make room for HLS and initialize it
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# make room for HLS and initialize it
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addi sp, sp, -64 // MENTRY_FRAME_SIZE
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addi sp, sp, -64 // MENTRY_FRAME_SIZE
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csrr a0, mhartid
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csrr a0, mhartid
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call hls_init
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call hls_init
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//poison the stack
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# poison the stack
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li t1, STACK_START
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li t1, STACK_START
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li t0, 0xdeadbeef
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li t0, 0xdeadbeef
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sd t0, 0(t1)
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sd t0, 0(t1)
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la t0, exception_handler
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la t0, trap_entry
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csrw mtvec, t0
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csrw mtvec, t0
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# clear any pending interrupts
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# clear any pending interrupts
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csrwi mip, 0
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csrwi mip, 0
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# set up the mstatus register for VM
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# set up the mstatus register for VM
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call mstatus_init
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call mstatus_init
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call main
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tail main
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.=0x2000
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.space 0x800
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# sbi interface lives here
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# hart_id
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.align 5
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li a7, 0
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ecall
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ret
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# num_harts
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.align 4
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li a0, 1
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ret
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# query_memory
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.align 4
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li a7, 8
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ecall
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ret
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# console_putchar
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.align 4
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li a7, 1
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ecall
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ret
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# send_device_request
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.align 4
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li a7, 2
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ecall
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ret
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# receive_device_response
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.align 4
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li a7, 3
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ecall
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ret
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# send ipi
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.align 4
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li a7, 4
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ecall
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ret
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# clear ipi
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.align 4
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li a7, 5
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ecall
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ret
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# timebase
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.align 4
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li a0, 10000000 # temporary, we should provide the correct answer
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ret
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# shutdown
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.align 4
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li a7, 6
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ecall
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# set_timer
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.align 4
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li a7, 7
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ecall
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ret
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# end of SBI trampolines
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.=0x4000
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.stack:
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.align 8
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.space 0xf00
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.stacktop:
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.quad 0
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.align 3
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.stack_size:
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.quad 0xf00
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.globl test_trap
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exception_handler:
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call trap_handler
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reset:
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init_stack_loop:
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.word CONFIG_STACK_SIZE
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.section ".id", "a", %progbits
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.section ".id", "a", @progbits
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.globl __id_start
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// fix this bs later. What's wrong with the riscv gcc?
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__id_start:
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ver:
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.asciz "1" //COREBOOT_VERSION
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vendor:
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.asciz "ucb" //CONFIG_MAINBOARD_VENDOR
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part:
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.asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
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.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */
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.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */
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.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */
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.long CONFIG_ROM_SIZE /* Size of this romimage */
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.globl __id_end
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__id_end:
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.previous
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@ -0,0 +1,33 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <build.h>
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.section ".id", "a", %progbits
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.globl __id_start
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__id_start:
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ver:
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.asciz "1" //COREBOOT_VERSION
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vendor:
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.asciz "ucb" //CONFIG_MAINBOARD_VENDOR
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part:
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.asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
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.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */
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.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */
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.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */
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.long CONFIG_ROM_SIZE /* Size of this romimage */
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.globl __id_end
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__id_end:
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.previous
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