vendorcode/amd: Satisfy clang's bracing requirements
src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h:3688:7: error: suggest braces around initialization of subobject Change-Id: Id086a64205dfffa2d1324993f4164508b57b6993 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -4089,7 +4089,7 @@ BOOLEAN MemFS3DefConstructorRet (
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
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0
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{ 0 }
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};
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#endif
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#if OPTION_DDR3
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@ -4097,7 +4097,7 @@ BOOLEAN MemFS3DefConstructorRet (
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0
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
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0
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{ 0 }
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};
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#endif
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/*---------------------------------------------------------------------------------------------------
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@ -3921,7 +3921,7 @@ BOOLEAN MemFS3DefConstructorRet (
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0
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
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0
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{ 0 }
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};
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#endif
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#if OPTION_DDR3
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@ -3929,7 +3929,7 @@ BOOLEAN MemFS3DefConstructorRet (
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0
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
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0
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{ 0 }
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};
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#endif
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/*---------------------------------------------------------------------------------------------------
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@ -3677,7 +3677,7 @@ BOOLEAN MemFS3DefConstructorRet (
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0
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
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0
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{ 0 }
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};
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#endif
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#if OPTION_DDR3
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@ -3685,7 +3685,7 @@ BOOLEAN MemFS3DefConstructorRet (
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0
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
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0
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{ 0 }
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};
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#endif
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/*---------------------------------------------------------------------------------------------------
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@ -4747,7 +4747,7 @@ BOOLEAN MemFS3DefConstructorRet (
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
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0
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{ 0 }
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};
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#endif
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#if OPTION_DDR3
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@ -4755,7 +4755,7 @@ BOOLEAN MemFS3DefConstructorRet (
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0
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
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0
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{ 0 }
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};
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#endif
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/*---------------------------------------------------------------------------------------------------
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@ -1584,7 +1584,7 @@ BOOLEAN MemFS3DefConstructorRet (
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0
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
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0
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{ 0 }
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};
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#endif
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#if OPTION_DDR3
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@ -1592,7 +1592,7 @@ BOOLEAN MemFS3DefConstructorRet (
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0
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
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0
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{ 0 }
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};
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#endif
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/*---------------------------------------------------------------------------------------------------
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