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soc/intel/jasperlake: Update gpio_op.asl to ASL2.0 syntax 

This change updates gpio_op.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.

Change-Id: I3ec442ad85f408135642a112873231ce7d39524e
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
V Sowmya 2020-05-28 22:29:52 +05:30 committed by Patrick Georgi
parent 2267158776
commit 8e6fa57e52
1 changed files with 16 additions and 16 deletions
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32
src/soc/intel/jasperlake/acpi/gpio_op.asl
View File

@ -11,7 +11,7 @@ Method (GRXS, 1, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
And (PAD_CFG0_RX_STATE, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
Return (Local0) Return (Local0)
} }
@ -27,7 +27,7 @@ Method (GTXS, 1, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
And (PAD_CFG0_TX_STATE, VAL0, Local0) Local0 = PAD_CFG0_TX_STATE & VAL0
Return (Local0) Return (Local0)
} }
@ -43,7 +43,7 @@ Method (STXS, 1, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
Or (PAD_CFG0_TX_STATE, VAL0, VAL0) VAL0 = PAD_CFG0_TX_STATE | VAL0
} }
/* /*
@ -57,7 +57,7 @@ Method (CTXS, 1, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
And (Not (PAD_CFG0_TX_STATE), VAL0, VAL0) VAL0 = ~PAD_CFG0_TX_STATE & VAL0
} }
/* /*
@ -76,10 +76,10 @@ Method (GPMO, 2, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
Store (VAL0, Local0) Local0 = VAL0
And (Not (PAD_CFG0_MODE_MASK), Local0, Local0) Local0 = ~PAD_CFG0_MODE_MASK & Local0
And (ShiftLeft (Arg1, PAD_CFG0_MODE_SHIFT, Arg1), PAD_CFG0_MODE_MASK, Arg1) Arg1 = (Arg1 <<= PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK
Or (Local0, Arg1, VAL0) VAL0 = Local0 | Arg1
} }
/* /*
@ -97,10 +97,10 @@ Method (GTXE, 2, Serialized)
VAL0, 32 VAL0, 32
} }
If (LEqual (Arg1, 1)) { If (Arg1 == 1) {
And (Not (PAD_CFG0_TX_DISABLE), VAL0, VAL0) VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0
} ElseIf (LEqual (Arg1, 0)){ } ElseIf (Arg1 == 0){
Or (PAD_CFG0_TX_DISABLE, VAL0, VAL0) VAL0 = PAD_CFG0_TX_DISABLE | VAL0
} }
} }
@ -119,9 +119,9 @@ Method (GRXE, 2, Serialized)
VAL0, 32 VAL0, 32
} }
If (LEqual (Arg1, 1)) { If (Arg1 == 1) {
And (Not (PAD_CFG0_RX_DISABLE), VAL0, VAL0) VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0
} ElseIf (LEqual (Arg1, 0)){ } ElseIf (Arg1 == 0){
Or (PAD_CFG0_RX_DISABLE, VAL0, VAL0) VAL0 = PAD_CFG0_RX_DISABLE | VAL0
} }
} }