code reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
6463ae7f1b
commit
8e79fc3fa8
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@ -15,9 +15,9 @@ void check_pirq_routing_table(void)
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#if defined(IRQ_SLOT_COUNT)
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if (sizeof(intel_irq_routing_table) != intel_irq_routing_table.size) {
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printk_warning("Inconsistent IRQ routing table size (0x%x/0x%x)\n",
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sizeof(intel_irq_routing_table),
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intel_irq_routing_table.size
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);
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sizeof(intel_irq_routing_table),
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intel_irq_routing_table.size
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);
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intel_irq_routing_table.size=sizeof(intel_irq_routing_table);
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}
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#endif
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@ -30,23 +30,23 @@ void check_pirq_routing_table(void)
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sum += addr[i];
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printk_debug("%s:%6d:%s() - irq_routing_table located at: 0x%p\n",
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__FILE__, __LINE__, __FUNCTION__, addr);
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__FILE__, __LINE__, __FUNCTION__, addr);
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sum = rt->checksum - sum;
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if (sum != rt->checksum) {
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printk_warning("%s:%6d:%s() - "
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"checksum is: 0x%02x but should be: 0x%02x\n",
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__FILE__, __LINE__, __FUNCTION__, rt->checksum, sum);
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"checksum is: 0x%02x but should be: 0x%02x\n",
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__FILE__, __LINE__, __FUNCTION__, rt->checksum, sum);
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rt->checksum = sum;
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}
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if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION ||
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rt->size % 16 || rt->size < sizeof(struct irq_routing_table)) {
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printk_warning("%s:%6d:%s() - "
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"Interrupt Routing Table not valid\n",
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__FILE__, __LINE__, __FUNCTION__);
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"Interrupt Routing Table not valid\n",
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__FILE__, __LINE__, __FUNCTION__);
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return;
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}
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@ -56,8 +56,8 @@ void check_pirq_routing_table(void)
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if (sum) {
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printk_warning("%s:%6d:%s() - "
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"checksum error in irq routing table\n",
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__FILE__, __LINE__, __FUNCTION__);
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"checksum error in irq routing table\n",
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__FILE__, __LINE__, __FUNCTION__);
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}
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printk_info("done.\n");
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@ -47,6 +47,7 @@ struct lb_memory *write_tables(struct mem_range *mem, unsigned long *processor_m
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post_code(0x9a);
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check_pirq_routing_table();
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/* This table must be betweeen 0xf0000 & 0x100000 */
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rom_table_end = copy_pirq_routing_table(rom_table_end);
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rom_table_end = (rom_table_end + 1023) & ~1023;
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@ -136,8 +136,8 @@ void smp_write_bus(struct mp_config_table *mc,
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}
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void smp_write_ioapic(struct mp_config_table *mc,
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unsigned char id, unsigned char ver,
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unsigned long apicaddr)
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unsigned char id, unsigned char ver,
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unsigned long apicaddr)
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{
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struct mpc_config_ioapic *mpc;
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mpc = smp_next_mpc_entry(mc);
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@ -221,8 +221,8 @@ dir /pc80
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#dir /bioscall
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cpu k8 "cpu0"
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register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
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register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
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register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
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register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
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end
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cpu k8 "cpu1"
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@ -150,6 +150,7 @@ static void main(void)
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static const struct ht_chain ht_c[] = {
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{
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.udev = PCI_DEV(0, 0x18, 0),
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/* LDT2 */
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.upos = 0xc0,
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.devreg = 0xe0,
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},
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@ -179,7 +180,6 @@ static void main(void)
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setup_s2885_resource_map();
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needs_reset = setup_coherent_ht_domain();
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// needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
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needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
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if (needs_reset) {
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print_info("ht reset -\r\n");
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@ -20,16 +20,16 @@ const struct irq_routing_table intel_irq_routing_table = {
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
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{0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
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{0x1,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
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{0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
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{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
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{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
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{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
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{0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
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{0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
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{0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x03,(0x4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
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{0x06, 0|0, {{0x0, 0x0000}, {0x0, 0x0000}, {0x0, 0x0000}, {0x4, 0xdef8}}, 0, 0},
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{0x01, 0|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
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{0x05,(0x3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
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{0x05,(0x6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
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{0x04,(0x8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
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{0x04,(0x7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
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{0x06,(0xa<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
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{0x04,(0x9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
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{0x06,(0xb<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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{0x06,(0xc<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
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}
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};
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@ -6,19 +6,19 @@
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void *smp_write_config_table(void *v, unsigned long * processor_map)
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{
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static const char sig[4] = "PCMP";
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static const char sig[4] = "PCMP";
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static const char oem[8] = "TYAN ";
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static const char productid[12] = "S2885 ";
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struct mp_config_table *mc;
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unsigned char bus_num;
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unsigned char bus_isa;
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unsigned char bus_8111_0;
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unsigned char bus_8111_1;
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unsigned char bus_8131_1;
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unsigned char bus_8131_2;
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unsigned char bus_8111_1;
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unsigned char bus_8151_1;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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@ -38,81 +38,70 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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smp_write_processors(mc, processor_map);
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{
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{
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device_t dev;
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/* 8111 */
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dev = dev_find_slot(3, PCI_DEVFN(0x03,0));
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if (dev) {
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bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_isa++;
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printk_debug("bus_isa=%d\n",bus_isa);
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}
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else {
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} else {
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printk_debug("ERROR - could not find PCI 3:03.0, using defaults\n");
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bus_8111_1 = 6;
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bus_isa = 7;
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}
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/* 8131-1 */
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dev = dev_find_slot(3, PCI_DEVFN(0x01,0));
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if (dev) {
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bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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} else {
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printk_debug("ERROR - could not find PCI 3:01.0, using defaults\n");
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bus_8131_1 = 4;
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}
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/* 8131-2 */
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dev = dev_find_slot(3, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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} else {
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printk_debug("ERROR - could not find PCI 3:02.0, using defaults\n");
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bus_8131_2 = 5;
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}
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/* 8151 */
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/* 8151 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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printk_debug("bus_8151_1=%d\n",bus_8151_1);
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}
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else {
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} else {
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printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
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bus_8151_1 = 2;
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}
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}
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}
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/*Bus: Bus ID Type*/
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/* define bus and isa numbers */
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for(bus_num = 0; bus_num < bus_isa; bus_num++) {
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/*Bus: Bus ID Type*/
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/* define bus and isa numbers */
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for (bus_num = 0; bus_num < bus_isa; bus_num++) {
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smp_write_bus(mc, bus_num, "PCI ");
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}
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smp_write_bus(mc, bus_isa, "ISA ");
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/*I/O APICs: APIC ID Version State Address*/
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/*I/O APICs: APIC ID Version State Address*/
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smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
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{
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struct pci_dev *dev;
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uint32_t base;
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/* 8131-1 APIC */
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dev = dev_find_slot(3, PCI_DEVFN(0x1,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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base &= PCI_BASE_ADDRESS_MEM_MASK;
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smp_write_ioapic(mc, 3, 0x11, base);
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}
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/* 8131-2 APIC */
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dev = dev_find_slot(3, PCI_DEVFN(0x2,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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@ -121,77 +110,82 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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}
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}
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/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
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*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, 0x2, 0x5);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
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//??? What
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (4<<2)|3, 0x2, 0x13);
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//Onboard AMD AC97 Audio ???
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (4<<2)|1, 0x2, 0x11);
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// Onboard AMD USB
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13);
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/* ISA Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, 0x2, 0x5);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
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// AGP Display Adapter
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, 0x2, 0x10);
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/* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
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// Integrated SMBus 2.0
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
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// Integrated AMD AC97 Audio
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
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// Onboard Serial ATA
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11);
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//Onboard Firewire
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x2, 0x13);
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//Onboard Broadcom NIC
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0);
|
||||
// Integrated AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
|
||||
|
||||
//Slot 5 PCI 32
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x2, 0x13); //
|
||||
// Onboard Serial ATA
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11);
|
||||
// Onboard Firewire
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x2, 0x13);
|
||||
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, 0x3, 0x2);//
|
||||
// Onboard Broadcom NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x09<<2)|0, 0x3, 0x0);
|
||||
|
||||
//Slot 4 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, 0x3, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, 0x3, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|3, 0x3, 0x1);//
|
||||
// AGP Display Adapter
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, 0x2, 0x10);
|
||||
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x4, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x4, 0x3); //
|
||||
//Slot 5 PCI 32
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x2, 0x13);
|
||||
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, 0x4, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, 0x4, 0x0);//
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|0, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|1, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|2, 0x3, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|3, 0x3, 0x2);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
//Slot 4 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|0, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|1, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|2, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|3, 0x3, 0x1);
|
||||
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|0, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|1, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|2, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|3, 0x4, 0x3);
|
||||
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|0, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|1, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|2, 0x4, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|3, 0x4, 0x0);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -385,9 +385,9 @@ static struct setup_smp_result setup_smp(void)
|
|||
|
||||
clear_temp_row(0); /* delete temporary connection */
|
||||
|
||||
result.needs_reset = optimize_connection(
|
||||
NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
|
||||
NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
|
||||
result.needs_reset =
|
||||
optimize_connection(NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
|
||||
NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
|
||||
|
||||
#if CONFIG_MAX_CPUS > 2
|
||||
result.cpus=4;
|
||||
|
|
@ -451,7 +451,8 @@ static struct setup_smp_result setup_smp(void)
|
|||
NODE_HT(2), 0x80 + link_to_register(link_connection(2,3)),
|
||||
NODE_HT(3), 0x80 + link_to_register(link_connection(3,2)) );
|
||||
|
||||
#endif
|
||||
#endif /* CONFIG_MAX_CPUS > 2 */
|
||||
|
||||
print_debug_hex8(result.cpus);
|
||||
print_debug(" nodes initialized.\r\n");
|
||||
return result;
|
||||
|
|
@ -644,8 +645,10 @@ static int setup_coherent_ht_domain(void)
|
|||
result = setup_smp();
|
||||
result.cpus = verify_mp_capabilities(result.cpus);
|
||||
#endif
|
||||
|
||||
coherent_ht_finalize(result.cpus);
|
||||
result.needs_reset = apply_cpu_errata_fixes(result.cpus, result.needs_reset);
|
||||
|
||||
#if CONFIG_MAX_CPUS > 1 /* Why doesn't this work on the solo? */
|
||||
result.needs_reset = optimize_link_read_pointers(result.cpus, result.needs_reset);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -316,8 +316,7 @@ static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num)
|
|||
reset_needed = 0;
|
||||
next_unitid = 1;
|
||||
|
||||
|
||||
for(i=0;i<ht_c_num;i++) {
|
||||
for (i = 0; i < ht_c_num; i++) {
|
||||
uint32_t reg;
|
||||
uint8_t reg8;
|
||||
reg = pci_read_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg);
|
||||
|
|
|
|||
Loading…
Reference in New Issue