soc/intel/alderlake: mb/intel/sm: Add tcss code

Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during
silicon init.
Type-c aux lines DC bias changes are propagated from tigerlake
platform.

TEST=Verified superspeed pendrive detection on coldboot.

Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Deepti Deshatty 2021-05-12 17:45:37 +05:30 committed by Patrick Georgi
parent d5433afb28
commit 8e7facf343
4 changed files with 35 additions and 19 deletions

View File

@ -14,8 +14,7 @@ chip soc/intel/alderlake
# TCSS # TCSS
register "TcssAuxOri" = "1" register "TcssAuxOri" = "1"
register "IomTypeCPortPadCfg[0]" = "0x09020005" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}"
register "IomTypeCPortPadCfg[1]" = "0x09020006"
# Enable heci communication # Enable heci communication
register "HeciEnabled" = "1" register "HeciEnabled" = "1"

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@ -212,17 +212,14 @@ struct soc_intel_alderlake_config {
bool CnviBtAudioOffload; bool CnviBtAudioOffload;
/* /*
* IOM Port Config * These GPIOs will be programmed by the IOM to handle biasing of the
* If a port orientation needs to be controlled by the SOC this setting must be * Type-C aux (SBU) signals when certain alternate modes are used.
* updated to reflect the correct GPIOs being used for the SOC port flipping. * `pad_auxn_dc` should be assigned to the GPIO pad providing negative
* There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
* 0,1 are pull up and pull down for port 0 * `pad_auxp_dc` should be assigned to the GPIO providing positive bias
* 2,3 are pull up and pull down for port 1 * (name often contains `AUXP_DC` or `_AUX_P`).
* 4,5 are pull up and pull down for port 2
* 6,7 are pull up and pull down for port 3
* values to be programmed correspond to the GPIO family and offsets
*/ */
uint32_t IomTypeCPortPadCfg[8]; struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS];
/* /*
* SOC Aux orientation override: * SOC Aux orientation override:

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@ -12,6 +12,7 @@
#include <intelblocks/xdci.h> #include <intelblocks/xdci.h>
#include <intelpch/lockdown.h> #include <intelpch/lockdown.h>
#include <intelblocks/mp_init.h> #include <intelblocks/mp_init.h>
#include <intelblocks/tcss.h>
#include <soc/gpio_soc_defs.h> #include <soc/gpio_soc_defs.h>
#include <soc/intel/common/vbt.h> #include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
@ -94,6 +95,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
const struct microcode *microcode_file; const struct microcode *microcode_file;
size_t microcode_len; size_t microcode_len;
FSP_S_CONFIG *params = &supd->FspsConfig; FSP_S_CONFIG *params = &supd->FspsConfig;
FSPS_ARCH_UPD *pfsps_arch_upd = &supd->FspsArchUpd;
uint32_t enable_mask; uint32_t enable_mask;
struct device *dev; struct device *dev;
@ -129,8 +131,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->D3ColdEnable = !config->TcssD3ColdDisable; params->D3ColdEnable = !config->TcssD3ColdDisable;
params->TcssAuxOri = config->TcssAuxOri; params->TcssAuxOri = config->TcssAuxOri;
for (i = 0; i < 8; i++)
params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; /* Explicitly clear this field to avoid using defaults */
memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));
/* /*
* Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
@ -189,6 +192,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
} }
/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
pfsps_arch_upd->EnableMultiPhaseSiliconInit = 1;
/* Enable xDCI controller if enabled in devicetree and allowed */ /* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (dev) { if (dev) {
@ -298,11 +304,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
mainboard_silicon_init_params(params); mainboard_silicon_init_params(params);
} }
int soc_fsp_multi_phase_init_is_enable(void)
{
return 0;
}
/* /*
* Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
* This platform supports below MultiPhaseSIInit Phase(s): * This platform supports below MultiPhaseSIInit Phase(s):
@ -315,6 +316,13 @@ void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
switch (phase_index) { switch (phase_index) {
case 1: case 1:
/* TCSS specific initialization here */ /* TCSS specific initialization here */
printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
__FILE__, __func__);
if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
const config_t *config = config_of_soc();
tcss_configure(config->typec_aux_bias_pads);
}
break; break;
default: default:
break; break;

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@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _SOC_TCSS_H_
#define _SOC_TCSS_H_
/* IOM aux bias control registers in REGBAR MMIO space */
#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070
#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4)
#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088
#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4)
#endif /* _SOC_TCSS_H_ */