soc/intel/alderlake: mb/intel/sm: Add tcss code
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -14,8 +14,7 @@ chip soc/intel/alderlake
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# TCSS
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# TCSS
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register "TcssAuxOri" = "1"
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register "TcssAuxOri" = "1"
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register "IomTypeCPortPadCfg[0]" = "0x09020005"
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}"
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register "IomTypeCPortPadCfg[1]" = "0x09020006"
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# Enable heci communication
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# Enable heci communication
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register "HeciEnabled" = "1"
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register "HeciEnabled" = "1"
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@ -212,17 +212,14 @@ struct soc_intel_alderlake_config {
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bool CnviBtAudioOffload;
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bool CnviBtAudioOffload;
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/*
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/*
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* IOM Port Config
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* These GPIOs will be programmed by the IOM to handle biasing of the
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* If a port orientation needs to be controlled by the SOC this setting must be
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* Type-C aux (SBU) signals when certain alternate modes are used.
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* updated to reflect the correct GPIOs being used for the SOC port flipping.
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* `pad_auxn_dc` should be assigned to the GPIO pad providing negative
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* There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down
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* bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
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* 0,1 are pull up and pull down for port 0
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* `pad_auxp_dc` should be assigned to the GPIO providing positive bias
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* 2,3 are pull up and pull down for port 1
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* (name often contains `AUXP_DC` or `_AUX_P`).
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* 4,5 are pull up and pull down for port 2
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* 6,7 are pull up and pull down for port 3
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* values to be programmed correspond to the GPIO family and offsets
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*/
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*/
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uint32_t IomTypeCPortPadCfg[8];
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struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS];
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/*
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/*
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* SOC Aux orientation override:
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* SOC Aux orientation override:
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@ -12,6 +12,7 @@
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#include <intelblocks/xdci.h>
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#include <intelblocks/xdci.h>
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#include <intelpch/lockdown.h>
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#include <intelpch/lockdown.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/tcss.h>
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#include <soc/gpio_soc_defs.h>
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#include <soc/gpio_soc_defs.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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@ -94,6 +95,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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const struct microcode *microcode_file;
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const struct microcode *microcode_file;
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size_t microcode_len;
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size_t microcode_len;
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FSP_S_CONFIG *params = &supd->FspsConfig;
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FSP_S_CONFIG *params = &supd->FspsConfig;
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FSPS_ARCH_UPD *pfsps_arch_upd = &supd->FspsArchUpd;
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uint32_t enable_mask;
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uint32_t enable_mask;
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struct device *dev;
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struct device *dev;
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@ -129,8 +131,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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params->D3ColdEnable = !config->TcssD3ColdDisable;
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params->D3ColdEnable = !config->TcssD3ColdDisable;
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params->TcssAuxOri = config->TcssAuxOri;
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params->TcssAuxOri = config->TcssAuxOri;
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for (i = 0; i < 8; i++)
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params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i];
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/* Explicitly clear this field to avoid using defaults */
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memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));
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/*
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/*
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* Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
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* Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
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@ -189,6 +192,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
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params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
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}
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}
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/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
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pfsps_arch_upd->EnableMultiPhaseSiliconInit = 1;
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/* Enable xDCI controller if enabled in devicetree and allowed */
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
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dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
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if (dev) {
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if (dev) {
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@ -298,11 +304,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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mainboard_silicon_init_params(params);
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mainboard_silicon_init_params(params);
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}
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}
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int soc_fsp_multi_phase_init_is_enable(void)
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{
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return 0;
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}
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/*
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/*
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* Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
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* Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
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* This platform supports below MultiPhaseSIInit Phase(s):
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* This platform supports below MultiPhaseSIInit Phase(s):
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@ -315,6 +316,13 @@ void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
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switch (phase_index) {
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switch (phase_index) {
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case 1:
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case 1:
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/* TCSS specific initialization here */
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/* TCSS specific initialization here */
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printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
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__FILE__, __func__);
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if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
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const config_t *config = config_of_soc();
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tcss_configure(config->typec_aux_bias_pads);
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}
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break;
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break;
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default:
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default:
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break;
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break;
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _SOC_TCSS_H_
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#define _SOC_TCSS_H_
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/* IOM aux bias control registers in REGBAR MMIO space */
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#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070
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#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4)
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#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088
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#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4)
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#endif /* _SOC_TCSS_H_ */
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