1. Change CONFIG_DEBUG to DEBUG in util/x86emu/*
2. Make DEBUG depend on CONFIG_YABEL_DEBUG_FLAGS being nonzero Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
99f75793c1
commit
8e9234ffff
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@ -1 +0,0 @@
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# If you add something to this file, enable it in src/arch/i386/Makefile.inc first.
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@ -1,47 +0,0 @@
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#define __PRE_RAM__
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#if CONFIG_LOGICAL_CPUS && \
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(defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
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#include <cpu/x86/lapic/boot_cpu.c>
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#else
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#define boot_cpu(x) 1
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#endif
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#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
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#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
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#else
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static void bootblock_northbridge_init(void) { }
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#endif
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#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
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#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
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#else
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static void bootblock_southbridge_init(void) { }
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#endif
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static unsigned long findstage(char* target)
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{
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unsigned long entry;
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asm volatile (
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"mov $1f, %%esp\n\t"
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"jmp walkcbfs\n\t"
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"1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp");
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return entry;
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}
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static void call(unsigned long addr, unsigned long bist)
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{
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asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist));
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}
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static void main(unsigned long bist)
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{
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if (boot_cpu()) {
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bootblock_northbridge_init();
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bootblock_southbridge_init();
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}
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const char* target1 = "fallback/romstage";
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unsigned long entry;
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entry = findstage(target1);
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if (entry) call(entry, bist);
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asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
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}
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@ -1,37 +0,0 @@
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/* -*- asm -*-
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* $ $
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*
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*/
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/*
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* Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
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*
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* This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* Originally this code was part of ucl the data compression library
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* for upx the ``Ultimate Packer of eXecutables''.
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*
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* - Converted to gas assembly, and refitted to work with etherboot.
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* Eric Biederman 20 Aug 2002
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* - Merged the nrv2b decompressor into crt0.base of coreboot
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* Eric Biederman 26 Sept 2002
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*/
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#include <arch/asm.h>
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#include <arch/intel.h>
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#include <console/loglevel.h>
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/*
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* This is the entry code the code in .reset section
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* jumps to this address.
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*
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*/
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.section ".rom.data", "a", @progbits
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.section ".rom.text", "ax", @progbits
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intel_chip_post_macro(0x01) /* delay for chipsets */
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@ -1,363 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005 Eswar Nallusamy, LANL
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* Copyright (C) 2005 Tyan
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* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
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* Copyright (C) 2007 coresystems GmbH
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* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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* Copyright (C) 2008 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */
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#include <arch/intel.h>
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#define ROM_CODE_SEG 0x08
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#define ROM_DATA_SEG 0x10
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#define CACHE_RAM_CODE_SEG 0x18
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#define CACHE_RAM_DATA_SEG 0x20
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/* When we come here we are in protected mode. We expand the stack
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* and copy the data segment from ROM to the memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE: Aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.section .rom.text
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.align 4
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.globl protected_stage0
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protected_stage0:
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_stage0
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.globl __protected_stage0
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__protected_stage0:
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/* Save the BIST result. */
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movl %eax, %ebp
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intel_chip_post_macro(0x01)
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Restore the BIST value to %eax. */
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movl %ebp, %eax
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.align 4
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/* disable HyperThreading is done by eswar
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* the other is very similar to the AMD CAR, except remove amd specific msr
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*/
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#define CacheSize CONFIG_DCACHE_RAM_SIZE
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#define CacheBase CONFIG_DCACHE_RAM_BASE
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#include <cpu/x86/mtrr.h>
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/* Save the BIST result */
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movl %eax, %ebp
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CacheAsRam:
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/* Check whether the processor has HT capability */
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movl $01, %eax
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cpuid
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btl $28, %edx
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jnc NotHtProcessor
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bswapl %ebx
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cmpb $01, %bh
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jbe NotHtProcessor
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/* It is a HT processor; Send SIPI to the other logical processor
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* within this processor so that the CAR related common system
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* registers are programmed accordingly
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*/
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/* Use some register that is common to both logical processors
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* as semaphore. Refer Appendix B, Vol.3
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*/
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xorl %eax, %eax
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xorl %edx, %edx
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movl $0x250, %ecx
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wrmsr
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/* Figure out the logical AP's APIC ID; the following logic will work
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* only for processors with 2 threads.
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*
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* Refer to Vol 3. Table 7-1 for details about this logic
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*/
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movl $0xFEE00020, %esi
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movl (%esi), %ebx
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andl $0xFF000000, %ebx
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bswapl %ebx
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btl $0, %ebx
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jnc LogicalAP0
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andb $0xFE, %bl
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jmp SendSIPI
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LogicalAP0:
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orb $0x01, %bl
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SendSIPI:
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bswapl %ebx /* ebx - logical AP's APIC ID */
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/* Fill up the IPI command registers in the Local APIC mapped to
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* default address and issue SIPI to the other logical processor
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* within this processor die.
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*/
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RetrySIPI:
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movl %ebx, %eax
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movl $0xFEE00310, %esi
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movl %eax, (%esi)
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/* SIPI vector - F900:0000 */
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movl $0x000006F9, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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movl $0x30, %ecx
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SIPIDelay:
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pause
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decl %ecx
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jnz SIPIDelay
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movl (%esi), %eax
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andl $0x00001000, %eax
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jnz RetrySIPI
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/* Wait for the Logical AP to complete initialization */
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LogicalAPSIPINotdone:
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movl $0x250, %ecx
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rdmsr
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orl %eax, %eax
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jz LogicalAPSIPINotdone
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NotHtProcessor:
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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wrmsr
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/* Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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/* 0x06 is the WB IO type for a given 4k segment.
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* segs is the number of 4k segments in the area of the particular
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* register we want to use for CAR.
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* reg is the register where the IO type should be stored.
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*/
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.macro extractmask segs, reg
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.if \segs <= 0
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/* The xorl here is superfluous because at the point of first execution
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* of this macro, %eax and %edx are cleared. Later invocations of this
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* macro will have a monotonically increasing segs parameter.
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*/
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xorl \reg, \reg
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.elseif \segs == 1
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movl $0x06000000, \reg /* WB IO type */
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.elseif \segs == 2
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movl $0x06060000, \reg /* WB IO type */
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.elseif \segs == 3
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movl $0x06060600, \reg /* WB IO type */
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.elseif \segs >= 4
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movl $0x06060606, \reg /* WB IO type */
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.endif
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.endm
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/* size is the cache size in bytes we want to use for CAR.
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* windowoffset is the 32k-aligned window into CAR size
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*/
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.macro simplemask carsize, windowoffset
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/* DO NOT CHANGE THE FORMATTING of the two lines below! Whitespace is
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* interpreted as an argument delimiter by some versions of GNU as. */
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extractmask (((\carsize-\windowoffset)/0x1000)-4), %eax
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extractmask (((\carsize-\windowoffset)/0x1000)), %edx
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.endm
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#if CacheSize > 0x10000
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#error Invalid CAR size, must be at most 64k.
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#endif
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#if CacheSize < 0x1000
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#error Invalid CAR size, must be at least 4k. This is a processor limitation.
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#endif
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#if (CacheSize & (0x1000 - 1))
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#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
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#endif
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#if CacheSize > 0x8000
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/* enable caching for 32K-64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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simplemask CacheSize, 0x8000
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wrmsr
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#endif
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/* enable caching for 0-32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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simplemask CacheSize, 0
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wrmsr
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#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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#else
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $REAL_XIP_ROM_BASE, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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movl $0x203, %ecx
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movl $0x0000000f, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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/* Read the range with lodsl*/
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movl $CacheBase, %esi
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cld
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movl $(CacheSize>>2), %ecx
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize>>2), %ecx
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xorl %eax, %eax
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rep stosl
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/* TODO: make this a config variable */
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#if CARTEST
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/* check the cache as ram */
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movl $CacheBase, %esi
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movl $(CacheSize>>2), %ecx
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.xin1:
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movl %esi, %eax
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movl %eax, (%esi)
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decl %ecx
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je .xout1
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add $4, %esi
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jmp .xin1
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.xout1:
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movl $CacheBase, %esi
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// movl $(CacheSize>>2), %ecx
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movl $4, %ecx
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.xin1x:
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movl %esi, %eax
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movl $0x4000, %edx
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movb %ah, %al
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.testx1:
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outb %al, $0x80
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decl %edx
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jnz .testx1
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movl (%esi), %eax
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cmpb 0xff, %al
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je .xin2 /* dont show */
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movl $0x4000, %edx
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.testx2:
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outb %al, $0x80
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decl %edx
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jnz .testx2
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.xin2: decl %ecx
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je .xout1x
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add $4, %esi
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jmp .xin1x
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.xout1x:
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#endif
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movl $(CacheBase+CacheSize-4), %eax
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movl %eax, %esp
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/* Load a different set of data segments */
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movw $CACHE_RAM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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lout:
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/* Store zero for the pointer to the global variables. */
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pushl $0
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/* Restore the BIST result. */
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movl %ebp, %eax
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/* We need to set ebp? No need. */
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movl %esp, %ebp
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/* Third parameter: cpu #: 0 == BSP all other are APs.
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* 0 until SMP support is added.
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*/
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pushl $0
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/* Second parameter: init_detected */
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/* Store zero for the unused init_detected parameter. */
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pushl $0
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/* First parameter: bist */
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pushl %eax
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call main
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/* We will not go back. */
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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@ -1,143 +0,0 @@
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/* -*- asm -*-
|
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* $ $
|
||||
*
|
||||
*/
|
||||
|
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/*
|
||||
* Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* Originally this code was part of ucl the data compression library
|
||||
* for upx the ``Ultimate Packer of eXecutables''.
|
||||
*
|
||||
* - Converted to gas assembly, and refitted to work with etherboot.
|
||||
* Eric Biederman 20 Aug 2002
|
||||
* - Merged the nrv2b decompressor into crt0.base of coreboot
|
||||
* Eric Biederman 26 Sept 2002
|
||||
*/
|
||||
|
||||
|
||||
#include <arch/asm.h>
|
||||
#include <arch/intel.h>
|
||||
#include <console/loglevel.h>
|
||||
|
||||
/*
|
||||
* This is the entry code the code in .reset section
|
||||
* jumps to this address.
|
||||
*
|
||||
*/
|
||||
.section ".rom.data", "a", @progbits
|
||||
.section ".rom.text", "ax", @progbits
|
||||
|
||||
intel_chip_post_macro(0x01) /* delay for chipsets */
|
||||
|
||||
#include "crt0_includes.h"
|
||||
|
||||
#if CONFIG_USE_DCACHE_RAM == 0
|
||||
#ifndef CONSOLE_DEBUG_TX_STRING
|
||||
/* uses: esp, ebx, ax, dx */
|
||||
# define __CRT_CONSOLE_TX_STRING(string) \
|
||||
mov string, %ebx ; \
|
||||
CALLSP(crt_console_tx_string)
|
||||
|
||||
# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
|
||||
# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
|
||||
# else
|
||||
# define CONSOLE_DEBUG_TX_STRING(string)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* clear boot_complete flag */
|
||||
xorl %ebp, %ebp
|
||||
__main:
|
||||
CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
|
||||
|
||||
/*
|
||||
* Copy data into RAM and clear the BSS. Since these segments
|
||||
* isn\'t really that big we just copy/clear using bytes, not
|
||||
* double words.
|
||||
*/
|
||||
intel_chip_post_macro(0x11) /* post 11 */
|
||||
|
||||
cld /* clear direction flag */
|
||||
|
||||
/* copy coreboot from it's initial load location to
|
||||
* the location it is compiled to run at.
|
||||
* Normally this is copying from FLASH ROM to RAM.
|
||||
*/
|
||||
movl %ebp, %esi
|
||||
/* FIXME: look for a proper place for the stack */
|
||||
movl $0x4000000, %esp
|
||||
movl %esp, %ebp
|
||||
pushl %esi
|
||||
pushl $str_coreboot_ram_name
|
||||
call cbfs_and_run_core
|
||||
|
||||
.Lhlt:
|
||||
intel_chip_post_macro(0xee) /* post fe */
|
||||
hlt
|
||||
jmp .Lhlt
|
||||
|
||||
#ifdef __CRT_CONSOLE_TX_STRING
|
||||
/* Uses esp, ebx, ax, dx */
|
||||
crt_console_tx_string:
|
||||
mov (%ebx), %al
|
||||
inc %ebx
|
||||
cmp $0, %al
|
||||
jne 9f
|
||||
RETSP
|
||||
9:
|
||||
/* Base Address */
|
||||
#ifndef CONFIG_TTYS0_BASE
|
||||
#define CONFIG_TTYS0_BASE 0x3f8
|
||||
#endif
|
||||
/* Data */
|
||||
#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
|
||||
|
||||
/* Control */
|
||||
#define TTYS0_TBR TTYS0_RBR
|
||||
#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
|
||||
#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
|
||||
#define TTYS0_FCR TTYS0_IIR
|
||||
#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
|
||||
#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
|
||||
#define TTYS0_DLL TTYS0_RBR
|
||||
#define TTYS0_DLM TTYS0_IER
|
||||
|
||||
/* Status */
|
||||
#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
|
||||
#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
|
||||
#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
|
||||
|
||||
mov %al, %ah
|
||||
10: mov $TTYS0_LSR, %dx
|
||||
inb %dx, %al
|
||||
test $0x20, %al
|
||||
je 10b
|
||||
mov $TTYS0_TBR, %dx
|
||||
mov %ah, %al
|
||||
outb %al, %dx
|
||||
|
||||
jmp crt_console_tx_string
|
||||
#endif /* __CRT_CONSOLE_TX_STRING */
|
||||
|
||||
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
|
||||
.section ".rom.data"
|
||||
#if CONFIG_COMPRESS
|
||||
str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n"
|
||||
#else
|
||||
str_copying_to_ram: .string "Copying coreboot to RAM.\r\n"
|
||||
#endif
|
||||
str_pre_main: .string "Jumping to coreboot.\r\n"
|
||||
.previous
|
||||
|
||||
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
|
||||
|
||||
str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX
|
||||
.string "/coreboot_ram"
|
||||
|
||||
#endif /* CONFIG_USE_DCACHE_RAM */
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 1999 Ronald G. Minnich
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <arch/rom_segs.h>
|
||||
.code16
|
||||
.globl _stage0
|
||||
_stage0:
|
||||
cli
|
||||
|
||||
/* Save the BIST result. */
|
||||
movl %eax, %ebp;
|
||||
|
||||
/* thanks to kmliu@sis.com.tw for this TLB fix */
|
||||
/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
|
||||
* executing any further code. Even though paging is disabled we
|
||||
* could still get false address translations due to the TLB if we
|
||||
* didn't invalidate it.
|
||||
*/
|
||||
xorl %eax, %eax
|
||||
movl %eax, %cr3 /* Invalidate TLB. */
|
||||
|
||||
/* Switch to protected mode. */
|
||||
|
||||
/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
|
||||
* using BFD version 2.15.94.0.2.2 20041220 this works fine without all
|
||||
* the ld hackery and other things. So leave it as is with this comment.
|
||||
*/
|
||||
|
||||
data32 lgdt %cs:gdtptr
|
||||
|
||||
movl %cr0, %eax
|
||||
andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */
|
||||
orl $0x60000001, %eax /* CD, NW, PE = 1 */
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Restore BIST result. */
|
||||
movl %ebp, %eax
|
||||
|
||||
// port80_post(0x23)
|
||||
/* Now we are in protected mode. Jump to a 32 bit code segment. */
|
||||
data32 ljmp $ROM_CODE_SEG, $protected_stage0
|
||||
|
||||
/* I am leaving this weird jump in here in the event that future gas
|
||||
* bugs force it to be used.
|
||||
*/
|
||||
/* .byte 0x66 */
|
||||
.code32
|
||||
/* ljmp $ROM_CODE_SEG, $protected_stage0 */
|
||||
|
||||
/* .code16 */
|
||||
.align 4
|
||||
.globl gdt16
|
||||
gdt16 = . - _stage0
|
||||
gdt16x:
|
||||
.word gdt16xend - gdt16x -1 /* Compute the table limit. */
|
||||
.long gdt16x
|
||||
.word 0
|
||||
|
||||
/* selgdt 0x08, flat code segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x9b, 0xcf, 0x00
|
||||
|
||||
/* selgdt 0x10, flat data segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x93, 0xcf, 0x00
|
||||
gdt16xend:
|
||||
|
||||
/* From now on we are 32 bit. */
|
||||
.code32
|
||||
|
||||
/* We have two gdts where we could have one. That is ok.
|
||||
*
|
||||
* Let's not worry about this -- optimizing gdt is pointless since
|
||||
* we're only in it for a little bit.
|
||||
*
|
||||
* Btw. note the trick below: The GDT points to ITSELF, and the first
|
||||
* good descriptor is at offset 8. So you word-align the table, and
|
||||
* then because you chose 8, you get a nice 64-bit aligned GDT entry,
|
||||
* which is good as this is the size of the entry.
|
||||
* Just in case you ever wonder why people do this.
|
||||
*/
|
||||
.align 4
|
||||
.globl gdtptr
|
||||
.globl gdt_limit
|
||||
gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */
|
||||
|
||||
gdt:
|
||||
gdtptr:
|
||||
.word gdt_end - gdt -1 /* Compute the table limit. */
|
||||
.long gdt /* We know the offset. */
|
||||
.word 0
|
||||
|
||||
/* selgdt 0x08, flat code segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x9b, 0xcf, 0x00
|
||||
|
||||
/* selgdt 0x10, flat data segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x93, 0xcf, 0x00
|
||||
|
||||
/* selgdt 0x18, flat code segment for CAR */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x9b, 0xcf, 0x00
|
||||
|
||||
/* selgdt 0x20, flat data segment for CAR */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x93, 0xcf, 0x00
|
||||
gdt_end:
|
||||
|
||||
/* Reset vector. */
|
||||
|
||||
/*
|
||||
* RVECTOR: Size of reset vector, default is 0x10.
|
||||
* RESRVED: Size of vpd code, default is 0xf0.
|
||||
* BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b).
|
||||
*/
|
||||
|
||||
SEGMENT_SIZE = 0x10000
|
||||
RVECTOR = 0x00010
|
||||
|
||||
/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
|
||||
* I think we should leave it this way forever, as the bugs come and
|
||||
* go -- and come again.
|
||||
*
|
||||
* .code16
|
||||
* .section ".rom.text"
|
||||
*/
|
||||
.section ".reset", "ax"
|
||||
.globl _resetjump
|
||||
_resetjump:
|
||||
/* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */
|
||||
/* jmp _stage0 */
|
||||
.byte 0xe9
|
||||
.int _stage0 - ( . + 2 )
|
||||
|
||||
/* Note: The above jump is hand coded to work around bugs in binutils.
|
||||
* 5 bytes are used for a 3 byte instruction. This works because x86
|
||||
* is little endian and allows us to use supported 32 bit relocations
|
||||
* instead of the weird 16 bit relocations that binutils does not
|
||||
* handle consistenly between versions because they are used so rarely.
|
||||
*/
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
TARGET(binary)
|
||||
SECTIONS
|
||||
{
|
||||
/DISCARD/ : {
|
||||
*(.comment)
|
||||
*(.note.*)
|
||||
*(.note)
|
||||
}
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
_ROMTOP = 0xfffffff0;
|
||||
. = _ROMTOP;
|
||||
.resetvector . : {
|
||||
*(.reset)
|
||||
. = 15 ;
|
||||
BYTE(0x00);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
INPUT(coreboot_apc.rom)
|
||||
SECTIONS
|
||||
{
|
||||
.apcrom . : {
|
||||
_apcrom = .;
|
||||
coreboot_apc.rom(*)
|
||||
_eapcrom = .;
|
||||
}
|
||||
_iseg_apc = CONFIG_DCACHE_RAM_BASE;
|
||||
_eiseg_apc = _iseg_apc + SIZEOF(.apcrom);
|
||||
_liseg_apc = _apcrom;
|
||||
_eliseg_apc = _eapcrom;
|
||||
}
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
/*
|
||||
* Memory map:
|
||||
*
|
||||
* CONFIG_RAMBASE
|
||||
* : data segment
|
||||
* : bss segment
|
||||
* : heap
|
||||
* : stack
|
||||
* CONFIG_ROMBASE
|
||||
* : coreboot text
|
||||
* : readonly text
|
||||
*/
|
||||
/*
|
||||
* Bootstrap code for the STPC Consumer
|
||||
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Written by Johan Rydberg, based on work by Daniel Kahlin.
|
||||
* Rewritten by Eric Biederman
|
||||
*/
|
||||
/*
|
||||
* We use ELF as output format. So that we can
|
||||
* debug the code in some form.
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
|
||||
OUTPUT_ARCH(i386)
|
||||
|
||||
/*
|
||||
ENTRY(_start)
|
||||
*/
|
||||
|
||||
TARGET(binary)
|
||||
SECTIONS
|
||||
{
|
||||
. = CONFIG_ROMBASE;
|
||||
|
||||
/* This section might be better named .setup */
|
||||
.rom . : {
|
||||
_rom = .;
|
||||
*(.rom.text);
|
||||
*(.rom.data);
|
||||
*(.rodata.*);
|
||||
*(.rom.data.*);
|
||||
. = ALIGN(16);
|
||||
_erom = .;
|
||||
}
|
||||
|
||||
_lrom = LOADADDR(.rom);
|
||||
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.comment)
|
||||
*(.comment.*)
|
||||
*(.note)
|
||||
*(.note.*)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
/*
|
||||
* Memory map:
|
||||
*
|
||||
* CONFIG_RAMBASE
|
||||
* : data segment
|
||||
* : bss segment
|
||||
* : heap
|
||||
* : stack
|
||||
* CONFIG_ROMBASE
|
||||
* : coreboot text
|
||||
* : readonly text
|
||||
*/
|
||||
/*
|
||||
* Bootstrap code for the STPC Consumer
|
||||
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Written by Johan Rydberg, based on work by Daniel Kahlin.
|
||||
* Rewritten by Eric Biederman
|
||||
*/
|
||||
/*
|
||||
* We use ELF as output format. So that we can
|
||||
* debug the code in some form.
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
|
||||
OUTPUT_ARCH(i386)
|
||||
|
||||
/*
|
||||
ENTRY(_start)
|
||||
*/
|
||||
|
||||
TARGET(binary)
|
||||
SECTIONS
|
||||
{
|
||||
. = CONFIG_ROMBASE;
|
||||
|
||||
/* This section might be better named .setup */
|
||||
.rom . : {
|
||||
_rom = .;
|
||||
*(.rom.text);
|
||||
*(.rom.data);
|
||||
*(.rom.data.*);
|
||||
*(.rodata.*);
|
||||
. = ALIGN(16);
|
||||
_erom = .;
|
||||
}
|
||||
|
||||
_lrom = LOADADDR(.rom);
|
||||
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.comment)
|
||||
*(.note)
|
||||
*(.comment.*)
|
||||
*(.note.*)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
/*
|
||||
* Memory map:
|
||||
*
|
||||
* CONFIG_RAMBASE
|
||||
* : data segment
|
||||
* : bss segment
|
||||
* : heap
|
||||
* : stack
|
||||
* CONFIG_ROMBASE
|
||||
* : coreboot text
|
||||
* : readonly text
|
||||
*/
|
||||
/*
|
||||
* Bootstrap code for the STPC Consumer
|
||||
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Written by Johan Rydberg, based on work by Daniel Kahlin.
|
||||
* Rewritten by Eric Biederman
|
||||
*/
|
||||
/*
|
||||
* We use ELF as output format. So that we can
|
||||
* debug the code in some form.
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
|
||||
OUTPUT_ARCH(i386)
|
||||
|
||||
/*
|
||||
ENTRY(_start)
|
||||
*/
|
||||
|
||||
TARGET(binary)
|
||||
SECTIONS
|
||||
{
|
||||
. = CONFIG_ROMBASE;
|
||||
|
||||
/* cut _start into last 64k*/
|
||||
_x = .;
|
||||
. = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x;
|
||||
|
||||
/* This section might be better named .setup */
|
||||
.rom . : {
|
||||
_rom = .;
|
||||
*(.rom.text);
|
||||
*(.rom.data);
|
||||
*(.init.rodata.*);
|
||||
*(.init.text);
|
||||
*(.rodata.*);
|
||||
*(.rom.data.*);
|
||||
. = ALIGN(16);
|
||||
_erom = .;
|
||||
}
|
||||
|
||||
_lrom = LOADADDR(.rom);
|
||||
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.comment)
|
||||
*(.note)
|
||||
*(.comment.*)
|
||||
*(.note.*)
|
||||
}
|
||||
}
|
||||
|
|
@ -90,7 +90,7 @@ static u8 biosemu_inb(u16 port)
|
|||
u8 val;
|
||||
|
||||
val = inb(port);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (port != 0x40)
|
||||
printk("inb(0x%04x) = 0x%02x\n", port, val);
|
||||
#endif
|
||||
|
|
@ -104,7 +104,7 @@ static u16 biosemu_inw(u16 port)
|
|||
|
||||
val = inw(port);
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
printk("inw(0x%04x) = 0x%04x\n", port, val);
|
||||
#endif
|
||||
return val;
|
||||
|
|
@ -116,7 +116,7 @@ static u32 biosemu_inl(u16 port)
|
|||
|
||||
val = inl(port);
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
printk("inl(0x%04x) = 0x%08x\n", port, val);
|
||||
#endif
|
||||
return val;
|
||||
|
|
@ -124,7 +124,7 @@ static u32 biosemu_inl(u16 port)
|
|||
|
||||
static void biosemu_outb(u16 port, u8 val)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (port != 0x43)
|
||||
printk("outb(0x%02x, 0x%04x)\n", val, port);
|
||||
#endif
|
||||
|
|
@ -133,7 +133,7 @@ static void biosemu_outb(u16 port, u8 val)
|
|||
|
||||
static void biosemu_outw(u16 port, u16 val)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
printk("outw(0x%04x, 0x%04x)\n", val, port);
|
||||
#endif
|
||||
outw(val, port);
|
||||
|
|
@ -141,7 +141,7 @@ static void biosemu_outw(u16 port, u16 val)
|
|||
|
||||
static void biosemu_outl(u16 port, u32 val)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
printk("outl(0x%08x, 0x%04x)\n", val, port);
|
||||
#endif
|
||||
outl(val, port);
|
||||
|
|
@ -556,7 +556,7 @@ void run_bios(struct device * dev, unsigned long addr)
|
|||
push_word(X86_SS);
|
||||
push_word(X86_SP + 2);
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
//X86EMU_trace_on();
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ struct x86_fpu_registers {
|
|||
|
||||
#endif /* X86_FPU_SUPPORT */
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
# define DECODE_PRINTINSTR32(t,mod,rh,rl) \
|
||||
DECODE_PRINTF(t[(mod<<3)+(rh)]);
|
||||
# define DECODE_PRINTINSTR256(t,mod,rh,rl) \
|
||||
|
|
|
|||
|
|
@ -279,7 +279,7 @@ typedef struct {
|
|||
u32 mode;
|
||||
volatile int intr; /* mask of pending interrupts */
|
||||
volatile int debug;
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
int check;
|
||||
u16 saved_ip;
|
||||
u16 saved_cs;
|
||||
|
|
|
|||
|
|
@ -47,8 +47,10 @@
|
|||
#include <console/console.h>
|
||||
#undef printk
|
||||
#define printk(x...) do_printk(BIOS_DEBUG, x)
|
||||
#if defined(CONFIG_DEBUG) && (CONFIG_DEBUG == 0)
|
||||
#undef CONFIG_DEBUG
|
||||
#if defined(CONFIG_YABEL_DEBUG_FLAGS) && (CONFIG_YABEL_DEBUG_FLAGS != 0)
|
||||
#define DEBUG
|
||||
#else
|
||||
#undef DEBUG
|
||||
#endif
|
||||
|
||||
#ifdef SCITECH
|
||||
|
|
@ -164,7 +166,7 @@ void X86EMU_setMemBase(void *base, size_t size);
|
|||
void X86EMU_exec(void);
|
||||
void X86EMU_halt_sys(void);
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
#define HALT_SYS() \
|
||||
printk("halt_sys: in %s\n", __func__); \
|
||||
X86EMU_halt_sys();
|
||||
|
|
|
|||
|
|
@ -170,7 +170,7 @@ __run_interrupt = RELOCATED(.)
|
|||
1:
|
||||
.code16 /* 16 bit code from here on... */
|
||||
|
||||
// CONFIG_DEBUG
|
||||
// DEBUG
|
||||
movb $0xec, %al
|
||||
outb %al, $0x80
|
||||
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
|
||||
/*----------------------------- Implementation ----------------------------*/
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
static void print_encoded_bytes (u16 s, u16 o);
|
||||
static void print_decoded_instruction (void);
|
||||
|
|
@ -94,7 +94,7 @@ void disassemble_forward (u16 seg, u16 off, int n)
|
|||
* flag associated with the "execution", and we are using a copy
|
||||
* of the register struct. All the major opcodes, once fully
|
||||
* decoded, have the following two steps: TRACE_REGS(r,m);
|
||||
* SINGLE_STEP(r,m); which disappear if CONFIG_DEBUG is not defined to
|
||||
* SINGLE_STEP(r,m); which disappear if DEBUG is not defined to
|
||||
* the preprocessor. The TRACE_REGS macro expands to:
|
||||
*
|
||||
* if (debug&DEBUG_DISASSEMBLE)
|
||||
|
|
@ -364,7 +364,7 @@ int parse_line (char *s, int *ps, int *n)
|
|||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_DEBUG */
|
||||
#endif /* DEBUG */
|
||||
|
||||
void x86emu_dump_regs (void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -40,8 +40,8 @@
|
|||
#ifndef __X86EMU_DEBUG_H
|
||||
#define __X86EMU_DEBUG_H
|
||||
|
||||
//#define CONFIG_DEBUG 0
|
||||
//#undef CONFIG_DEBUG
|
||||
//#define DEBUG 0
|
||||
//#undef DEBUG
|
||||
/*---------------------- Macros and type definitions ----------------------*/
|
||||
|
||||
/* checks to be enabled for "runtime" */
|
||||
|
|
@ -51,7 +51,7 @@
|
|||
#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */
|
||||
#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F)
|
||||
# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F)
|
||||
# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F)
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
# define CHECK_DATA_ACCESS()
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F)
|
||||
# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F)
|
||||
# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F)
|
||||
|
|
@ -106,7 +106,7 @@
|
|||
# define DEBUG_DECODE_NOPRINT() 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \
|
||||
x86emu_decode_printf(x)
|
||||
|
|
@ -136,7 +136,7 @@
|
|||
# define SAVE_IP_CS(x,y)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
#define TRACE_REGS() \
|
||||
if (DEBUG_DISASSEMBLE()) { \
|
||||
x86emu_just_disassemble(); \
|
||||
|
|
@ -147,7 +147,7 @@
|
|||
# define TRACE_REGS()
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step()
|
||||
#else
|
||||
# define SINGLE_STEP()
|
||||
|
|
@ -157,7 +157,7 @@
|
|||
TRACE_REGS(); \
|
||||
SINGLE_STEP()
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
# define START_OF_INSTR()
|
||||
# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr();
|
||||
# define END_OF_INSTR_NO_TRACE() x86emu_end_instr();
|
||||
|
|
@ -167,7 +167,7 @@
|
|||
# define END_OF_INSTR_NO_TRACE()
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
# define CALL_TRACE(u,v,w,x,s) \
|
||||
if (DEBUG_TRACECALLREGS()) \
|
||||
x86emu_dump_regs(); \
|
||||
|
|
@ -189,7 +189,7 @@
|
|||
# define JMP_TRACE(u,v,w,x,s)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
#define DB(x) x
|
||||
#else
|
||||
#define DB(x)
|
||||
|
|
|
|||
|
|
@ -285,7 +285,7 @@ _INLINE u32 get_data_segment(void)
|
|||
case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS:
|
||||
return M.x86.R_SS;
|
||||
default:
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
printk("error: should not happen: multiple overrides.\n");
|
||||
#endif
|
||||
HALT_SYS();
|
||||
|
|
@ -305,7 +305,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline!
|
|||
u8 fetch_data_byte(
|
||||
uint offset)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access((u16)get_data_segment(), offset);
|
||||
#endif
|
||||
|
|
@ -324,7 +324,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline!
|
|||
u16 fetch_data_word(
|
||||
uint offset)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access((u16)get_data_segment(), offset);
|
||||
#endif
|
||||
|
|
@ -343,7 +343,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline!
|
|||
u32 fetch_data_long(
|
||||
uint offset)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access((u16)get_data_segment(), offset);
|
||||
#endif
|
||||
|
|
@ -364,7 +364,7 @@ u8 fetch_data_byte_abs(
|
|||
uint segment,
|
||||
uint offset)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access(segment, offset);
|
||||
#endif
|
||||
|
|
@ -385,7 +385,7 @@ u16 fetch_data_word_abs(
|
|||
uint segment,
|
||||
uint offset)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access(segment, offset);
|
||||
#endif
|
||||
|
|
@ -406,7 +406,7 @@ u32 fetch_data_long_abs(
|
|||
uint segment,
|
||||
uint offset)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access(segment, offset);
|
||||
#endif
|
||||
|
|
@ -428,7 +428,7 @@ void store_data_byte(
|
|||
uint offset,
|
||||
u8 val)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access((u16)get_data_segment(), offset);
|
||||
#endif
|
||||
|
|
@ -450,7 +450,7 @@ void store_data_word(
|
|||
uint offset,
|
||||
u16 val)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access((u16)get_data_segment(), offset);
|
||||
#endif
|
||||
|
|
@ -472,7 +472,7 @@ void store_data_long(
|
|||
uint offset,
|
||||
u32 val)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access((u16)get_data_segment(), offset);
|
||||
#endif
|
||||
|
|
@ -495,7 +495,7 @@ void store_data_byte_abs(
|
|||
uint offset,
|
||||
u8 val)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access(segment, offset);
|
||||
#endif
|
||||
|
|
@ -518,7 +518,7 @@ void store_data_word_abs(
|
|||
uint offset,
|
||||
u16 val)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access(segment, offset);
|
||||
#endif
|
||||
|
|
@ -541,7 +541,7 @@ void store_data_long_abs(
|
|||
uint offset,
|
||||
u32 val)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (CHECK_DATA_ACCESS())
|
||||
x86emu_check_data_access(segment, offset);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1))
|
|||
END_OF_INSTR_NO_TRACE();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
static char *x86emu_fpu_op_d9_tab[] = {
|
||||
"FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ",
|
||||
|
|
@ -89,7 +89,7 @@ static char *x86emu_fpu_op_d9_tab1[] = {
|
|||
"FRNDINT", "FSCALE", "ESC_D9", "ESC_D9",
|
||||
};
|
||||
|
||||
#endif /* CONFIG_DEBUG */
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* opcode=0xd9 */
|
||||
void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1))
|
||||
|
|
@ -100,7 +100,7 @@ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1))
|
|||
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (mod != 3) {
|
||||
DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl);
|
||||
} else {
|
||||
|
|
@ -294,7 +294,7 @@ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1))
|
|||
END_OF_INSTR_NO_TRACE();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
char *x86emu_fpu_op_da_tab[] = {
|
||||
"FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ",
|
||||
|
|
@ -316,7 +316,7 @@ char *x86emu_fpu_op_da_tab[] = {
|
|||
"ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ",
|
||||
};
|
||||
|
||||
#endif /* CONFIG_DEBUG */
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* opcode=0xda */
|
||||
void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1))
|
||||
|
|
@ -384,7 +384,7 @@ void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1))
|
|||
END_OF_INSTR_NO_TRACE();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
char *x86emu_fpu_op_db_tab[] = {
|
||||
"FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ",
|
||||
|
|
@ -397,7 +397,7 @@ char *x86emu_fpu_op_db_tab[] = {
|
|||
"ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ",
|
||||
};
|
||||
|
||||
#endif /* CONFIG_DEBUG */
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* opcode=0xdb */
|
||||
void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1))
|
||||
|
|
@ -407,7 +407,7 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1))
|
|||
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (mod != 3) {
|
||||
DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl);
|
||||
} else if (rh == 4) { /* === 11 10 0 nnn */
|
||||
|
|
@ -428,7 +428,7 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1))
|
|||
} else {
|
||||
DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl));
|
||||
}
|
||||
#endif /* CONFIG_DEBUG */
|
||||
#endif /* DEBUG */
|
||||
switch (mod) {
|
||||
case 0:
|
||||
destoffset = decode_rm00_address(rl);
|
||||
|
|
@ -504,7 +504,7 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1))
|
|||
END_OF_INSTR_NO_TRACE();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
char *x86emu_fpu_op_dc_tab[] = {
|
||||
"FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ",
|
||||
"FCOMP\tQWORD PTR ",
|
||||
|
|
@ -524,7 +524,7 @@ char *x86emu_fpu_op_dc_tab[] = {
|
|||
"FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t",
|
||||
"FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t",
|
||||
};
|
||||
#endif /* CONFIG_DEBUG */
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* opcode=0xdc */
|
||||
void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1))
|
||||
|
|
@ -618,7 +618,7 @@ void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1))
|
|||
END_OF_INSTR_NO_TRACE();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
static char *x86emu_fpu_op_dd_tab[] = {
|
||||
"FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ",
|
||||
|
|
@ -634,7 +634,7 @@ static char *x86emu_fpu_op_dd_tab[] = {
|
|||
"ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,",
|
||||
};
|
||||
|
||||
#endif /* CONFIG_DEBUG */
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* opcode=0xdd */
|
||||
void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1))
|
||||
|
|
@ -718,7 +718,7 @@ void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1))
|
|||
END_OF_INSTR_NO_TRACE();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
static char *x86emu_fpu_op_de_tab[] =
|
||||
{
|
||||
|
|
@ -741,7 +741,7 @@ static char *x86emu_fpu_op_de_tab[] =
|
|||
"FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t",
|
||||
};
|
||||
|
||||
#endif /* CONFIG_DEBUG */
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* opcode=0xde */
|
||||
void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1))
|
||||
|
|
@ -837,7 +837,7 @@ void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1))
|
|||
END_OF_INSTR_NO_TRACE();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
static char *x86emu_fpu_op_df_tab[] = {
|
||||
/* mod == 00 */
|
||||
|
|
@ -860,7 +860,7 @@ static char *x86emu_fpu_op_df_tab[] = {
|
|||
"ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F,"
|
||||
};
|
||||
|
||||
#endif /* CONFIG_DEBUG */
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* opcode=0xdf */
|
||||
void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1))
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@
|
|||
|
||||
/* constant arrays to do several instructions in just one function */
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
static char *x86emu_GenOpName[8] = {
|
||||
"ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"};
|
||||
#endif
|
||||
|
|
@ -157,7 +157,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) =
|
|||
sar_long,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
static char *opF6_names[8] =
|
||||
{ "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" };
|
||||
|
|
@ -1285,7 +1285,7 @@ static void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -1361,7 +1361,7 @@ static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -1471,7 +1471,7 @@ static void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -1545,7 +1545,7 @@ static void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -3127,7 +3127,7 @@ static void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -3202,7 +3202,7 @@ static void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -3679,7 +3679,7 @@ static void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -3750,7 +3750,7 @@ static void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -3852,7 +3852,7 @@ static void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -3925,7 +3925,7 @@ static void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1))
|
|||
*/
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -4928,7 +4928,7 @@ static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1))
|
|||
/* Yet another special case instruction. */
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
@ -4994,7 +4994,7 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
|
|||
/* Yet another special case instruction. */
|
||||
START_OF_INSTR();
|
||||
FETCH_DECODE_MODRM(mod, rh, rl);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
if (DEBUG_DECODE()) {
|
||||
/* XXX DECODE_PRINTF may be changed to something more
|
||||
general, so that it is important to leave the strings
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad
|
|||
{
|
||||
u8 *rom_image;
|
||||
int i = 0;
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
debug_flags = 0;//DEBUG_PRINT_INT10 | DEBUG_PNP | DEBUG_INTR | DEBUG_CHECK_VMEM_ACCESS | DEBUG_MEM | DEBUG_IO;
|
||||
// | DEBUG_CHECK_VMEM_ACCESS | DEBUG_MEM | DEBUG_IO;
|
||||
// | DEBUG_TRACE_X86EMU | DEBUG_JMP;
|
||||
|
|
@ -252,7 +252,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad
|
|||
CHECK_DBG(DEBUG_TRACE_X86EMU) {
|
||||
X86EMU_trace_on();
|
||||
} else {
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
M.x86.debug |= DEBUG_SAVE_IP_CS_F;
|
||||
M.x86.debug |= DEBUG_DECODE_F;
|
||||
M.x86.debug |= DEBUG_DECODE_NOPRINT_F;
|
||||
|
|
@ -273,7 +273,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad
|
|||
* some boot device status in AX (see PNP BIOS Spec Section 3.3
|
||||
*/
|
||||
DEBUG_PRINTF_CS_IP("Option ROM Exit Status: %04x\n", M.x86.R_AX);
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
DEBUG_PRINTF("Exit Status Decode:\n");
|
||||
if (M.x86.R_AX & 0x100) { // bit 8
|
||||
DEBUG_PRINTF
|
||||
|
|
|
|||
|
|
@ -69,9 +69,9 @@ static inline void set_ci(void) {};
|
|||
// set to enable tracing of JMPs in x86emu
|
||||
#define DEBUG_JMP 0x2000
|
||||
|
||||
//#define CONFIG_DEBUG
|
||||
//#undef CONFIG_DEBUG
|
||||
#ifdef CONFIG_DEBUG
|
||||
//#define DEBUG
|
||||
//#undef DEBUG
|
||||
#ifdef DEBUG
|
||||
|
||||
#define CHECK_DBG(_flag) if (debug_flags & _flag)
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ static inline void set_ci(void) {};
|
|||
#define DEBUG_PRINTF_DISK(_x...)
|
||||
#define DEBUG_PRINTF_PNP(_x...)
|
||||
|
||||
#endif //CONFIG_DEBUG
|
||||
#endif //DEBUG
|
||||
|
||||
void dump(u8 * addr, u32 len);
|
||||
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@ biosemu_dev_get_addr_info(void)
|
|||
}
|
||||
// store last entry index of translate_address_array
|
||||
taa_last_entry = taa_index - 1;
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
//dump translate_address_array
|
||||
printf("translate_address_array: \n");
|
||||
translate_address_t ta;
|
||||
|
|
@ -195,7 +195,7 @@ biosemu_dev_get_addr_info(void)
|
|||
}
|
||||
// store last entry index of translate_address_array
|
||||
taa_last_entry = taa_index - 1;
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
//dump translate_address_array
|
||||
printf("translate_address_array: \n");
|
||||
translate_address_t ta;
|
||||
|
|
@ -334,7 +334,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr)
|
|||
memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset),
|
||||
sizeof(pci_ds));
|
||||
clr_ci();
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
DEBUG_PRINTF("PCI Data Structure @%lx:\n",
|
||||
rom_base_addr + pci_ds_offset);
|
||||
dump((void *) &pci_ds, sizeof(pci_ds));
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
#include "compat/time.h"
|
||||
|
||||
// define a check for access to certain (virtual) memory regions (interrupt handlers, BIOS Data Area, ...)
|
||||
#ifdef CONFIG_DEBUG
|
||||
#ifdef DEBUG
|
||||
static u8 in_check = 0; // to avoid recursion...
|
||||
u16 ebda_segment;
|
||||
u32 ebda_size;
|
||||
|
|
|
|||
Loading…
Reference in New Issue