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soc/intel/tigerlake: Fix FSP SPD index for DDR4 

For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1
to set SPD for index 4. This change adds a helper macro to translate
DDR4 channel # to the index # that the FSP expects.

BUG=b:154445630
TEST=Verified that memory initialization for DDR4 is successful.

Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Furquan Shaikh 2020-04-21 23:19:52 -07:00
parent 5d76958de1
commit 8ebbe17b86
1 changed files with 9 additions and 1 deletions
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10
src/soc/intel/tigerlake/meminit.c
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@ -16,6 +16,14 @@
#define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \ #define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \
((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2))) ((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2)))
/*
* Translate DDR4 channel # to FSP UPD index # for the channel.
* Channel 0 -> Index 0
* Channel 1 -> Index 4
* Index 1-3 and 5-7 are unused.
*/
#define DDR4_FSP_UPD_CHANNEL_IDX(x) ((x) * 4)
enum dimm_enable_options { enum dimm_enable_options {
ENABLE_BOTH_DIMMS = 0, ENABLE_BOTH_DIMMS = 0,
DISABLE_DIMM0 = 1, DISABLE_DIMM0 = 1,
@ -378,7 +386,7 @@ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg,
for (i = 0; i < DDR4_CHANNELS; i++) { for (i = 0; i < DDR4_CHANNELS; i++) {
ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info, ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info,
half_populated, &spd_dimm0, &spd_dimm1); half_populated, &spd_dimm0, &spd_dimm1);
init_spd_upds(mem_cfg, i, spd_dimm0, spd_dimm1); init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1);
} }
/* /*