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armv7: move armv7_invalidate_caches() to cache.c 

This just moves cache maintenance stuff from the armv7 bootblock
code to cache.c

Change-Id: I0b3ab58a1d8a3fe3d9568e02e156a36b6f33ca0b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2867
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
David Hendricks 2013-03-19 17:11:31 -07:00
parent eb06a4259b
commit 8ec69053f1
3 changed files with 52 additions and 52 deletions
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52
src/arch/armv7/bootblock_simple.c
View File

@ -28,58 +28,6 @@
#include "stages.c"
static void armv7_invalidate_caches(void)
{
uint32_t clidr;
int level;
/* Invalidate branch predictor */
bpiall();
/* Iterate thru each cache identified in CLIDR and invalidate */
clidr = read_clidr();
for (level = 0; level < 7; level++) {
unsigned int ctype = (clidr >> (level * 3)) & 0x7;
uint32_t csselr;
switch(ctype) {
case 0x0:
/* no cache */
break;
case 0x1:
/* icache only */
csselr = (level << 1) | 1;
write_csselr(csselr);
icache_invalidate_all();
break;
case 0x2:
case 0x4:
/* dcache only or unified cache */
dcache_invalidate_all();
break;
case 0x3:
/* separate icache and dcache */
csselr = (level << 1) | 1;
write_csselr(csselr);
icache_invalidate_all();
csselr = level < 1;
write_csselr(csselr);
dcache_invalidate_all();
break;
default:
/* reserved */
break;
}
}
/* Invalidate TLB */
/* FIXME: ARMv7 Architecture Ref. Manual claims that the distinction
* instruction vs. data TLBs is deprecated in ARMv7. But that doesn't
* really seem true for Cortex-A15? */
tlb_invalidate_all();
}
static int boot_cpu(void)
{
/*

3
src/arch/armv7/include/arch/cache.h
View File

@ -225,6 +225,9 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
/* invalidate entire icache on current level (given by CSSELR) */
void icache_invalidate_all(void);
/* invalidate all caches on ARMv7 */
void armv7_invalidate_caches(void);
/* MMU setup by machine virtual address */
void mmu_setup_by_mva(unsigned long start, unsigned long size);

49
src/arch/armv7/lib/cache.c
View File

@ -170,6 +170,55 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
dccimvac(addr);
}
void armv7_invalidate_caches(void)
{
uint32_t clidr;
int level;
/* Invalidate branch predictor */
bpiall();
/* Iterate thru each cache identified in CLIDR and invalidate */
clidr = read_clidr();
for (level = 0; level < 7; level++) {
unsigned int ctype = (clidr >> (level * 3)) & 0x7;
uint32_t csselr;
switch(ctype) {
case 0x0:
/* no cache */
break;
case 0x1:
/* icache only */
csselr = (level << 1) | 1;
write_csselr(csselr);
icache_invalidate_all();
break;
case 0x2:
case 0x4:
/* dcache only or unified cache */
dcache_invalidate_all();
break;
case 0x3:
/* separate icache and dcache */
csselr = (level << 1) | 1;
write_csselr(csselr);
icache_invalidate_all();
csselr = level < 1;
write_csselr(csselr);
dcache_invalidate_all();
break;
default:
/* reserved */
break;
}
}
/* Invalidate TLB */
tlb_invalidate_all();
}
/* FIXME: wrapper around imported mmu_setup() for now */
extern void mmu_setup(unsigned long start, unsigned long size);
void mmu_setup_by_mva(unsigned long start, unsigned long size)