soc/amd/sabrina: Allow to specify custom SPL File

PSP needs SPL file to boot. Introduce the support to add SPL file.
Currently Sabrina does not have a specific SPL file. Use Cezanne SPL
file as a placeholder.

BUG=b:224618411
TEST=Build and boot to OS in Skyrim after adding Sabrina specific SPL
file.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63313
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/sabrina/Kconfig

@@ -387,6 +387,23 @@ config PSP_WHITELIST_FILE
 	depends on HAVE_PSP_WHITELIST_FILE
 	default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin"
 
+config HAVE_SPL_FILE
+	bool "Have a mainboard specific SPL table file"
+	default n
+	help
+	  Have a mainboard specific Security Patch Level (SPL) table file. SPL file
+	  is required to support PSP FW anti-rollback and needs to be created by AMD.
+	  The default SPL file applies to all boards that use the concerned SoC and
+	  is dropped under 3rdparty/blobs. The mainboard specific SPL file override
+	  can be applied through SPL_TABLE_FILE config.
+
+	  If unsure, answer 'n'
+
+config SPL_TABLE_FILE
+	string "SPL table file"
+	depends on HAVE_SPL_FILE
+	default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin"
+
 config PSP_SOFTFUSE_BITS
 	string "PSP Soft Fuse bits to enable"
 	default "28 6"

src/soc/amd/sabrina/Makefile.inc

@@ -119,6 +119,11 @@ ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y)
 PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
 endif
 
+# type = 0x55
+ifeq ($(CONFIG_HAVE_SPL_FILE),y)
+SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE)
+endif
+
 #
 # BIOS Directory Table items - proper ordering is managed by amdfwtool
 #
@@ -188,6 +193,7 @@ OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --
 OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
 
 OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
+OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
 
 # If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant
 OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy)
@@ -208,6 +214,7 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 		--combo-capable \
 		$(OPT_TOKEN_UNLOCK) \
 		$(OPT_WHITELIST_FILE) \
+		$(OPT_SPL_TABLE_FILE) \
 		$(OPT_PSP_SHAREDMEM_BASE) \
 		$(OPT_PSP_SHAREDMEM_SIZE) \
 		$(OPT_EFS_SPI_READ_MODE) \

src/soc/amd/sabrina/fw.cfg

@@ -30,6 +30,7 @@ UNIFIEDUSB_FILE         TypeId0x44_UnifiedUsb_CZN.sbin
 DRTMTA_FILE             TypeId0x47_DrtmTA_CZN.sbin
 KEYDBBL_FILE            TypeId0x50_KeyDbBl_CZN.sbin
 KEYDB_TOS_FILE          TypeId0x51_KeyDbTos_CZN.sbin
+SPL_TABLE_FILE          TypeId0x55_SplTableBl_CZN.sbin
 DMCUERAMDCN21_FILE      TypeId0x58_DmcuEramDcn21.sbin
 DMCUINTVECTORSDCN21_FILE  TypeId0x59_DmcuIntvectorsDcn21.sbin
 PSPBTLDR_AB_FILE        TypeId0x73_PspBootLoader_AB_CZN.sbin