GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb,soc/amd/*/northbridge: use mmio_range to add IOAPIC2 resources 

Instead of open coding this, use the mmio_range helper function to tell
the resource allocator about the northbridge's IOAPIC's MMIO. This
change sets the IORESOURCE_RESERVE and IORESOURCE_STORED bits in the
resource flags that weren't set before, but mmio_range is already used
elsewhere for similar purposes.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id66a73cdb22fd551e4359914ba5513313dcc3193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Felix Held 2023-08-09 19:28:39 +02:00 committed by Martin L Roth
parent 38880d236f
commit 8f0075c379
2 changed files with 2 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -158,8 +158,6 @@ static void add_fixed_resources(struct device *dev, int index)
static void nb_read_resources(struct device *dev) static void nb_read_resources(struct device *dev)
{ {
struct resource *res;
/* /*
* This MMCONF resource must be reserved in the PCI domain. * This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in * It is not honored by the coreboot resource allocator if it is in
@ -168,10 +166,7 @@ static void nb_read_resources(struct device *dev)
mmconf_resource(dev, MMIO_CONF_BASE); mmconf_resource(dev, MMIO_CONF_BASE);
/* NB IOAPIC2 resource */ /* NB IOAPIC2 resource */
res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ mmio_range(dev, IO_APIC2_ADDR, IO_APIC2_ADDR, 0x1000);
res->base = IO_APIC2_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
add_fixed_resources(dev, 0); add_fixed_resources(dev, 0);
} }

6
src/soc/amd/stoneyridge/northbridge.c
View File

@ -59,7 +59,6 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
static void read_resources(struct device *dev) static void read_resources(struct device *dev)
{ {
unsigned int idx = 0; unsigned int idx = 0;
struct resource *res;
/* The northbridge has no PCI BARs implemented, so there's no need to call /* The northbridge has no PCI BARs implemented, so there's no need to call
pci_dev_read_resources for it */ pci_dev_read_resources for it */
@ -72,10 +71,7 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++); mmconf_resource(dev, idx++);
/* NB IOAPIC2 resource */ /* NB IOAPIC2 resource */
res = new_resource(dev, idx++); /* IOAPIC2 */ mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000);
res->base = IO_APIC2_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
static void set_resource(struct device *dev, struct resource *res, u32 nodeid) static void set_resource(struct device *dev, struct resource *res, u32 nodeid)