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soraka: Ensure I2C5 frequency is less than 400kHz 

Update I2C5 bus parameters to obtain clock frequency <400kHz.

BUG=b:65062416
TEST=Verified using an oscilloscope that I2C5 bus frequency
in factory is ~397kHz.

Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-09-24 20:50:14 -07:00 committed by Furquan Shaikh
parent 3a182f7e31
commit 8f08f5f5c7
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/poppy/variants/soraka/devicetree.cb
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@ -226,8 +226,8 @@ chip soc/intel/skylake
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.speed_config[0] = { .speed_config[0] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.scl_lcnt = 180, .scl_lcnt = 195,
.scl_hcnt = 80, .scl_hcnt = 90,
.sda_hold = 36, .sda_hold = 36,
}, },
}" }"