soc/amd/genoa: Add Kconfig/Makefile to generate PSP image
TESTED: AMD onyx reaches x86 code Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76498 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Arthur Heymans
Felix Held
parent
6f4a9497ae
commit
8f1c707060
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## SPDX-License-Identifier: GPL-2.0-only
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ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/Typex60_0_0_0_Apcb.bin),)
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APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/Typex60_0_0_0_Apcb.bin
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APCB_SOURCES1 = $(MAINBOARD_BLOBS_DIR)/Typex60_0_1_0_Apcb.bin
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APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/Typex68_0_0_0_ApcbRec.bin
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APCB_SOURCES_RECOVERY1 = $(MAINBOARD_BLOBS_DIR)/Typex68_0_8_0_ApcbRec.bin
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APCB_SOURCES_RECOVERY2 = $(MAINBOARD_BLOBS_DIR)/Typex68_0_9_0_ApcbRec.bin
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else
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files_added:: warn_no_apcb
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endif
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@ -74,4 +74,62 @@ config ROMSTAGE_SIZE
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help
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Sets the size of DRAM allocation for romstage in linker script.
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endif
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menu "PSP Configuration Options"
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config AMDFW_CONFIG_FILE
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string
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default "src/soc/amd/genoa/fw.cfg"
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config PSP_DISABLE_POSTCODES
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bool "Disable PSP post codes"
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help
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Disables the output of port80 post codes from PSP.
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config PSP_INIT_ESPI
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bool "Initialize eSPI in PSP Stage 2 Boot Loader"
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help
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Select to initialize the eSPI controller in the PSP Stage 2 Boot
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Loader.
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config PSP_UNLOCK_SECURE_DEBUG
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bool
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default y
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config HAVE_PSP_WHITELIST_FILE
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bool "Include a debug whitelist file in PSP build"
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default n
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help
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Support secured unlock prior to reset using a whitelisted
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serial number. This feature requires a signed whitelist image
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and bootloader from AMD.
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If unsure, answer 'n'
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config PSP_WHITELIST_FILE
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string "Debug whitelist file path"
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depends on HAVE_PSP_WHITELIST_FILE
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config HAVE_SPL_FILE
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bool
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config SPL_TABLE_FILE
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string "SPL table file"
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depends on HAVE_SPL_FILE
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default "3rdparty/amd_blobs_internal/genoa/PSP/Typex55_0_0_0_BLAntiRB.bin"
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config PSP_SOFTFUSE_BITS
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string "PSP Soft Fuse bits to enable"
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default ""
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help
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Space separated list of Soft Fuse bits to enable.
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Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
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Bit 7: Disable PSP postcodes on Renoir and newer chips only
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(Set by PSP_DISABLE_PORT80)
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Bit 15: PSP debug output destination:
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0=SoC MMIO UART, 1=IO port 0x3F8
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See #57299 (NDA) for additional bit definitions.
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endmenu
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endif # SOC_AMD_GENOA
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@ -14,4 +14,124 @@ ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1)
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CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000
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endif
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#
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# PSP Directory Table items
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#
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# Certain ordering requirements apply, however these are ensured by amdfwtool.
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# For more information see "AMD Platform Security Processor BIOS Implementation
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# Guide for Server EPYC Processors" #57299
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#
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FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
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ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
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PSP_SOFTFUSE_BITS += 7
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endif
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ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
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# Enable secure debug unlock
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PSP_SOFTFUSE_BITS += 0
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OPT_TOKEN_UNLOCK="--token-unlock"
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endif
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# Use additional Soft Fuse bits specified in Kconfig
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PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS))
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# type = 0x3a
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ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y)
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PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
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endif
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# type = 0x55
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ifeq ($(CONFIG_HAVE_SPL_FILE),y)
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SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE)
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endif
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#
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# BIOS Directory Table items - proper ordering is managed by amdfwtool
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#
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# type = 0x60
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PSP_APCB_FILES=$(APCB_SOURCES) $(APCB1_SOURCES) $(APCB_SOURCES_RECOVERY) $(APCB_SOURCES_RECOVERY1) $(APCB_SOURCES_RECOVERY2)
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# type = 0x61
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PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
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# type = 0x62
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PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
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PSP_ELF_FILE=$(objcbfs)/bootblock.elf
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PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
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PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
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# Helper function to return a value with given bit set
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# Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions.
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set-bit=$(call int-shift-left, 1 $(call _toint,$1))
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PSP_SOFTFUSE=$(shell A=$(call int-add, \
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$(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A)
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#
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# Build the arguments to amdfwtool (order is unimportant). Missing file names
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# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool.
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#
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add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
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OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \
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$(if $(APCB_SOURCES1), --instance 1 --apcb $(APCB_SOURCES1)) \
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$(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \
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$(if $(APCB_SOURCES_RECOVERY1), --instance 18 --apcb $(APCB_SOURCES_RECOVERY1)) \
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$(if $(APCB_SOURCES_RECOVERY2), --instance 19 --apcb $(APCB_SOURCES_RECOVERY2)) \
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$(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
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OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
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OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
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OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
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OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
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OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
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OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
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OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
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OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
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OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
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OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
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AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
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$(OPT_APOB_ADDR) \
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$(OPT_DEBUG_AMDFWTOOL) \
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$(OPT_PSP_BIOSBIN_FILE) \
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$(OPT_PSP_BIOSBIN_DEST) \
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$(OPT_PSP_BIOSBIN_SIZE) \
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$(OPT_PSP_SOFTFUSE) \
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--use-pspsecureos \
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$(OPT_TOKEN_UNLOCK) \
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$(OPT_WHITELIST_FILE) \
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$(OPT_SPL_TABLE_FILE) \
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$(OPT_EFS_SPI_READ_MODE) \
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$(OPT_EFS_SPI_SPEED) \
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$(OPT_EFS_SPI_MICRON_FLAG) \
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--config $(CONFIG_AMDFW_CONFIG_FILE) \
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--flashsize 0x1000000
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$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
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$$(PSP_APCB_FILES) \
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$(DEP_FILES) \
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$(AMDFWTOOL) \
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$(obj)/fmap_config.h \
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$(objcbfs)/bootblock.elf # this target also creates the .map file
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$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
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rm -f $@
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@printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n"
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$(AMDFWTOOL) \
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$(AMDFW_COMMON_ARGS) \
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--location $(CONFIG_AMD_FWM_POSITION) \
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--multilevel \
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--output $@
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$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
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rm -f $@
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@printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n"
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$(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
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--maxsize $(PSP_BIOSBIN_SIZE)
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endif
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@ -0,0 +1,54 @@
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# PSP fw config file
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FIRMWARE_LOCATION 3rdparty/amd_blobs/genoa/PSP
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SOC_NAME Genoa
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# type file
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# PSP
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AMD_PUBKEY_FILE Typex0_0_0_0_AmdPubKey.bin
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PSPBTLDR_FILE Typex1_0_0_0_PspBootLoader.bin Lbb
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PSPRCVR_FILE Typex3_0_0_0_PspRecBL.bin
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PSP_SMUFW1_SUB0_FILE Typex8_0_0_0_Smu.bin
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PSP_SMUFW1_SUB1_FILE Typex8_0_0_1_Smu.bin
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PSP_SMUFW1_SUB2_FILE Typex8_0_0_2_Smu.bin
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PSPSECUREDEBUG_FILE Typex9_0_0_0_DbgKey.bin
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PSP_OEM_ABL_KEY_FILE Typexa_0_0_0_OemAblKey.bin
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PSP_SMUFW2_SUB0_FILE Typex12_0_0_0_Smu2.bin
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PSP_SMUFW2_SUB1_FILE Typex12_0_0_1_Smu2.bin
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PSP_SMUFW2_SUB2_FILE Typex12_0_0_2_Smu2.bin Lbb
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PSP_SEC_DEBUG_FILE Typex13_0_0_0_PspEarlyUnlock.bin Lbb
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PSP_IKEK_FILE Typex21_0_0_0_ikek.bin
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PSP_TOKEN_UNLOCK_FILE Typex22_0_0_0_PspTokenUnlockData.bin
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PSP_SECG0_FILE Typex24_0_0_0_SecureGasket.bin
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PSP_SECG1_FILE Typex24_0_0_1_SecureGasket.bin
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PSP_SECG2_FILE Typex24_0_0_2_SecureGasket.bin
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PSP_MP5FW_SUB0_FILE Typex2a_0_0_0_Mp5Fw.bin
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PSP_MP5FW_SUB1_FILE Typex2a_0_0_1_Mp5Fw.bin
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PSP_MP5FW_SUB2_FILE Typex2a_0_0_2_Mp5Fw.bin
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PSP_ABL0_FILE Typex30_0_0_0_PspAgesaBL0.bin
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SEV_CODE_FILE Typex39_0_0_0_SevCode.bin
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SEV_DATA_FILE Typex38_0_0_0_SevData.bin
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PSP_DXIOFW_FILE Typex42_0_0_0_DxioFw.bin
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UNIFIEDUSB_FILE Typex44_0_0_0_UsbPhyFw.bin
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DRTMTA_FILE Typex47_0_0_0_DrtmTa.bin
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KEYDBBL_FILE Typex50_0_0_0_PspBlPubKey.bin
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SPL_TABLE_FILE Typex55_0_0_0_BLAntiRB.bin Lbb
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PSP_MPIOFW_FILE Typex5d_0_0_0_MPIOOffchipFW.bin
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PSP_RIB_FILE_SUB0 Typex76_0_0_0_RIB.bin
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PSP_MPDMATFFW_FILE Typex8c_0_0_0_MpdmaTfFw.bin
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PSP_GMI3PHYFW_FILE Typex91_0_0_0_Gmi3PhyFw.bin
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PSP_MPDMAPMFW_FILE Typex92_0_0_0_MpdmaPmFw.bin
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AMD_FUSE_CHAIN Dummy Lbb
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# BDT
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PSP_PMUI_FILE_SUB0_INS3 Typex64_0_3_0_PmuCode.bin
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PSP_PMUI_FILE_SUB0_INS4 Typex64_0_4_0_PmuCode.bin
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PSP_PMUI_FILE_SUB0_INS9 Typex64_0_9_0_PmuCode.bin
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PSP_PMUI_FILE_SUB0_INSA Typex64_0_a_0_PmuCode.bin
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PSP_PMUI_FILE_SUB0_INSB Typex64_0_b_0_PmuCode.bin
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PSP_PMUD_FILE_SUB0_INS3 Typex65_0_3_0_PmuData.bin
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PSP_PMUD_FILE_SUB0_INS4 Typex65_0_4_0_PmuData.bin
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PSP_PMUD_FILE_SUB0_INS9 Typex65_0_9_0_PmuData.bin
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PSP_PMUD_FILE_SUB0_INSA Typex65_0_a_0_PmuData.bin
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PSP_PMUD_FILE_SUB0_INSB Typex65_0_b_0_PmuData.bin
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PSP_PMUD_FILE_SUB0_INSC Typex65_0_c_0_PmuData.bin
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# TODO: Typex69_0_0_0_EarlyVgaImage.bin
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