soc/intel/cannonlake: Fix and clean up xhci ACPI code
During S3 cycling, system entered S3 only once and falied to enter S3 the second time. The system gets stuck at this point and we have to do a cold reboot to restore the system. Since XHCI IP is able to power gate during kernel freeze/suspend, this patch removes unnecessary device gating from ASL. This helps in continuous cycling of S3. BUG=b:69115421 TEST=run powerd_dbus_suspend multiple times and check if the system enters and resumes from S3. Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Vaibhav Shankar
Aaron Durbin
parent
f0349023a2
commit
8f20044c77
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@ -16,54 +16,6 @@
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*/
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*/
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#include <soc/gpe.h>
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#include <soc/gpe.h>
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/*
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* USB Port Wake Enable (UPWE) on usb attach/detach
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* Arg0 - Port Number
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* Arg1 - Port 1 Status and control offset
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* Arg2 - xHCI Memory-mapped address
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*/
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Method (UPWE, 3, Serialized)
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{
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/* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */
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Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0)
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/* Map ((XMEM << 16) + Local0 in PSCR */
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OperationRegion (PSCR, SystemMemory,
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Add (ShiftLeft (Arg2, 16), Local0), 0x10)
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Field (PSCR, AnyAcc, NoLock, Preserve)
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{
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, 25,
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UPCE, 1,
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UPDE, 1,
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}
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Store (One, UPCE)
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Store (One, UPDE)
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}
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/*
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* USB Wake Enable Setup (UWES)
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* Arg0 - Port enable bitmap
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* Arg1 - Port 1 Status and control offset
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* Arg2 - xHCI Memory-mapped address
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*/
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Method (UWES, 3, Serialized)
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{
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Store (Arg0, Local0)
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While (One) {
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FindSetRightBit (Local0, Local1)
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If (LEqual (Local1, Zero)) {
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Break
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}
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UPWE (Local1, Arg1, Arg2)
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/*
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* Clear the lowest set bit in Local0 since it was
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* processed.
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* Local0 = Local0 & (Local0 - 1)
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*/
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And (Local0, Subtract (Local0, 1), Local0)
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}
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}
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/* XHCI Controller 0:14.0 */
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/* XHCI Controller 0:14.0 */
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@ -73,112 +25,18 @@ Device (XHCI)
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Name (_PRW, Package () { GPE0_PME_B0, 3 })
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Name (_PRW, Package () { GPE0_PME_B0, 3 })
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Method (_DSW, 3)
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{
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Store (Arg0, PMEE)
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UWES (And (\U2WE, 0x3FF), 0x480, XMEM)
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UWES (And (\U3WE, 0x3F), 0x540, XMEM)
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}
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Name (_S3D, 3) /* D3 supported in S3 */
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Name (_S3D, 3) /* D3 supported in S3 */
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Name (_S4D, 3) /* D3 supported in S4 */
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Name (_S0W, 3) /* D3 can wake device in S0 */
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Name (_S0W, 3) /* D3 can wake device in S0 */
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Name (_S3W, 3) /* D3 can wake system from S3 */
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Name (_S3W, 3) /* D3 can wake system from S3 */
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Name (_S4W, 3) /* D3 can wake system from S4 */
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OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
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Field (XPRT, AnyAcc, NoLock, Preserve)
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{
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Offset (0x0),
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DVID, 16, /* VENDORID */
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Offset (0x10),
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, 16,
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XMEM, 16, /* MEM_BASE */
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Offset (0x50), /* XHCLKGTEN */
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, 2,
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STGE, 1, /* SS Link Trunk clock gating enable */
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Offset (0x74),
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D0D3, 2, /* POWERSTATE */
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, 6,
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PMEE, 1, /* PME_EN */
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, 6,
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PMES, 1, /* PME_STS */
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Offset (0xA2),
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, 2,
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D3HE, 1, /* D3_hot_en */
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}
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OperationRegion (XREG, SystemMemory,
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Add (ShiftLeft (XMEM, 16), 0x8000), 0x200)
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Field (XREG, DWordAcc, Lock, Preserve)
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{
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Offset (0x1c4), /* USB2PMCTRL */
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, 2,
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UPSW, 2, /* U2PSUSPGP */
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}
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Method (_PSC, 0, Serialized)
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{
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Return (^D0D3)
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}
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Method (_PS0, 0, Serialized)
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Method (_PS0, 0, Serialized)
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{
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{
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If (LEqual (^DVID, 0xFFFF)) {
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Return
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}
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If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
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Return
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}
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/* Disable d3hot and SS link trunk clock gating */
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Store(Zero, ^D3HE)
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Store(Zero, ^STGE)
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/* If device is in D3, set back to D0 */
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If (LEqual (^D0D3, 3)) {
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Store (Zero, Local0)
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Store (Local0, ^D0D3)
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Store (^D0D3, Local0)
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}
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/* Disable USB2 PHY SUS Well Power Gating */
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Store (Zero, ^UPSW)
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}
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}
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Method (_PS3, 0, Serialized)
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Method (_PS3, 0, Serialized)
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{
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{
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If (LEqual (^DVID, 0xFFFF)) {
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Return
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}
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If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
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Return
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}
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/* Clear PME Status */
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Store (1, ^PMES)
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/* Enable PME */
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Store (1, ^PMEE)
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/* If device is in D3, set back to D0 */
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If (LEqual (^D0D3, 3)) {
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Store (Zero, Local0)
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Store (Local0, ^D0D3)
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Store (^D0D3, Local0)
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}
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/* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */
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Store (3, ^UPSW)
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/* Enable d3hot and SS link trunk clock gating */
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Store(One, ^D3HE)
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Store(One, ^STGE)
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/* Now put device in D3 */
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Store (3, Local0)
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Store (Local0, ^D0D3)
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Store (^D0D3, Local0)
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}
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}
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/* Root Hub for Cannonlake-LP PCH */
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/* Root Hub for Cannonlake-LP PCH */
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