No warnings day, next round.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/Kconfig

@@ -621,7 +621,8 @@ config DEBUG_SMBUS
 	depends on (SOUTHBRIDGE_VIA_VT8237R \
 		 || NORTHBRIDGE_VIA_VX800 \
 		 || NORTHBRIDGE_VIA_CX700 \
-		 || NORTHBRIDGE_AMD_AMDK8)
+		 || NORTHBRIDGE_AMD_AMDK8 \
+		 || NORTHBRIDGE_AMD_AMDFAM10)
 	help
 	  This option enables additional SMBus (and SPD) debug messages.
 

src/cpu/amd/model_10xxx/init_cpus.c

@@ -91,7 +91,7 @@ static void set_pci_mmio_conf_reg(void)
 	wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
 
 	//mtrr for that range?
-//	set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
+	// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
 
 	set_wrap32dis();
 
@@ -293,7 +293,7 @@ static void enable_apic_ext_id(u32 node)
 }
 
 
-static void STOP_CAR_AND_CPU()
+static void STOP_CAR_AND_CPU(void)
 {
 	msr_t msr;
 
@@ -529,7 +529,7 @@ static void setup_remote_node(u8 node)
 }
 #endif	/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
-void AMD_Errata281(u8 node, u32 revision, u32 platform)
+static void AMD_Errata281(u8 node, u32 revision, u32 platform)
 {
 	/* Workaround for Transaction Scheduling Conflict in
 	 * Northbridge Cross Bar.  Implement XCS Token adjustment
@@ -591,7 +591,7 @@ void AMD_Errata281(u8 node, u32 revision, u32 platform)
 }
 
 
-void AMD_Errata298(void)
+static void AMD_Errata298(void)
 {
 	/* Workaround for L2 Eviction May Occur during operation to
 	 * set Accessed or dirty bit.

src/cpu/amd/model_fxx/model_fxx_init.c

@@ -244,7 +244,6 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
 static void init_ecc_memory(unsigned node_id)
 {
 	unsigned long startk, begink, endk;
-	unsigned long hole_startk = 0;
 	unsigned long basek;
 	struct mtrr_state mtrr_state;
 
@@ -291,6 +290,8 @@ static void init_ecc_memory(unsigned node_id)
 	endk   = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
+	unsigned long hole_startk = 0;
+
 	#if CONFIG_K8_REV_F_SUPPORT == 0
         if (!is_cpu_pre_e0())
 	{

src/cpu/amd/model_lx/cpureginit.c

@@ -25,7 +25,7 @@
 ;*	SetDelayControl
 ;*
 ;*************************************************************************/
-void SetDelayControl(void)
+static void SetDelayControl(void)
 {
 	unsigned int msrnum, glspeed;
 	unsigned char spdbyte0, spdbyte1;

src/cpu/x86/mtrr/earlymtrr.c

@@ -4,37 +4,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 
-/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
+#if 0
-#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
-# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
-#endif
-#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
-# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
-#endif
-#if !defined(CONFIG_RAMTOP)
-# error "CONFIG_RAMTOP not defined"
-#endif
-
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
-# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
-#endif
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
-# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
-#endif
-
-#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
-# error "CONFIG_RAMTOP must be a power of 2"
-#endif
-
-#if defined(CONFIG_XIP_ROM_SIZE)
-# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-   extern unsigned long AUTO_XIP_ROM_BASE;
-#  define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-# else
-#  define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-# endif
-#endif
-
 static void disable_var_mtrr(unsigned reg)
 {
 	/* The invalid bit is kept in the mask so we simply
@@ -45,6 +15,7 @@ static void disable_var_mtrr(unsigned reg)
 	zero.lo = zero.hi = 0;
 	wrmsr(MTRRphysMask_MSR(reg), zero);
 }
+#endif
 
 static void set_var_mtrr(
 	unsigned reg, unsigned base, unsigned size, unsigned type)
@@ -61,6 +32,7 @@ static void set_var_mtrr(
 	wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
+#if 0
 static void set_var_mtrr_x(
         unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
 
@@ -79,6 +51,7 @@ static void set_var_mtrr_x(
 	}
         wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
+#endif
 
 static void cache_lbmem(int type)
 {

src/include/cpu/x86/cache.h

@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2004 Eric W. Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #ifndef CPU_X86_CACHE
 #define CPU_X86_CACHE
 
@@ -17,6 +36,7 @@ static inline void invd(void)
 {
 	asm volatile("invd" ::: "memory");
 }
+
 static inline void wbinvd(void)
 {
 	asm volatile ("wbinvd");

src/include/cpu/x86/mtrr.h

@@ -31,7 +31,6 @@
 #define MTRRfix4K_F0000_MSR 0x26e
 #define MTRRfix4K_F8000_MSR 0x26f
 
-
 #if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 #include <device/device.h>
 void enable_fixed_mtrr(void);
@@ -42,5 +41,39 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
 void x86_setup_fixed_mtrrs(void);
 #endif
 
+/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
+#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
+# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
+#endif
+#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
+# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
+#endif
+#if !defined(CONFIG_RAMTOP)
+# error "CONFIG_RAMTOP not defined"
+#endif
+
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
+# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
+#endif
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
+# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
+#endif
+
+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
+# error "CONFIG_RAMTOP must be a power of 2"
+#endif
+
+
+#if !defined (ASSEMBLY)
+#if defined(CONFIG_XIP_ROM_SIZE)
+# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+   extern unsigned long AUTO_XIP_ROM_BASE;
+#  define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+# else
+#  define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+# endif
+#endif
+
+#endif
 
 #endif /* CPU_X86_MTRR_H */

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -58,18 +58,13 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 
 #include <console/loglevel.h>
-#if 0
-void die(const char *msg);
-int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk(BIOS_EMERG, fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
-#endif
-#define printk(BIOS_INFO, fmt, arg...)   do_printk(BIOS_INFO   ,fmt, ##arg)
 #include "cpu/x86/bist.h"
 
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #include "southbridge/amd/rs780/rs780_early_setup.c"

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -29,20 +29,11 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if 0 
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
 #include "pc80/serial.c"
 #include "console/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include <reset.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 
@@ -54,7 +45,8 @@ static void post_code(uint8_t value) {
 #include "lib/delay.c"
 
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/asus/a8n_e/mptable.c

@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
 	static const char productid[12] = "A8N-E      ";
 	struct mp_config_table *mc;
 	unsigned sbdn;
-	int i, bus_num;
+	int bus_num;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	memset(mc, 0, sizeof(*mc));

src/mainboard/asus/a8n_e/romstage.c

@@ -96,7 +96,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-	unsigned value;
 	uint32_t dword;
 	uint8_t byte;
 

src/mainboard/asus/a8v-e_se/romstage.c

@@ -187,7 +187,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	int needs_reset = 0;
 	struct sys_info *sysinfo =
 	    (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-	char *p;
 
 	sio_init();
 	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/intel/d945gclf/Makefile.inc

@@ -17,11 +17,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
 obj-y += rtl8168.o
 
-
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

src/mainboard/kontron/986lcd-m/Makefile.inc

@@ -17,11 +17,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
 obj-y += rtl8168.o
 
-
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

src/mainboard/roda/rk886ex/Makefile.inc

@@ -17,13 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
-##
-## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
-##
-
 obj-y += m3885.o
 obj-y += ec.o
 obj-y += rtl8168.o
 
-
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

src/mainboard/tyan/s4880/romstage.c

@@ -56,7 +56,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_HUB 0x18
-        int ret;
         unsigned device=(ctrl->channel0[0])>>8;
         smbus_write_byte(SMBUS_HUB, 0x01, device);
         smbus_write_byte(SMBUS_HUB, 0x03, 0);

src/northbridge/amd/amdk8/amdk8_f.h

@@ -520,6 +520,8 @@ struct sys_info {
 
 #include <reset.h>
 
+#if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \
+	((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__))
 static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 {
 
@@ -585,5 +587,6 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 	}
 
 }
+#endif
 
 #endif /* AMDK8_F_H */

src/northbridge/amd/amdk8/misc_control.c

@@ -110,7 +110,7 @@ static void misc_control_init(struct device *dev)
 {
 	uint32_t cmd, cmd_ref;
 	int needs_reset;
-	struct device *f0_dev, *f2_dev;
+	struct device *f0_dev;
 	
 	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 	needs_reset = 0;
@@ -161,6 +161,7 @@ static void misc_control_init(struct device *dev)
 		}
 	}
 	else if(is_cpu_pre_d0()) {
+		struct device *f2_dev;
 		uint32_t dcl;
 		f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
 		/* Errata 98 

src/northbridge/amd/amdk8/raminit.c

@@ -18,10 +18,6 @@
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
-#if defined (__GNUC__)
-static void hard_reset(void);
-#endif
-
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;

src/northbridge/amd/amdk8/raminit_f.c

@@ -707,12 +707,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	printk(BIOS_SPEW, "done.\n");
 }
 
+#if 0
 static int is_dual_channel(const struct mem_controller *ctrl)
 {
 	uint32_t dcl;
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	return dcl & DCL_Width128;
 }
+#endif
 
 static int is_opteron(const struct mem_controller *ctrl)
 {
@@ -727,6 +729,7 @@ static int is_opteron(const struct mem_controller *ctrl)
 	return !!(nbcap & NBCAP_128Bit);
 }
 
+#if 0
 static int is_registered(const struct mem_controller *ctrl)
 {
 	/* Test to see if we are dealing with registered SDRAM.
@@ -737,7 +740,7 @@ static int is_registered(const struct mem_controller *ctrl)
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	return !(dcl & DCL_UnBuffDimm);
 }
-
+#endif
 
 static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
 {
@@ -2481,6 +2484,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
 
+#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
 static void set_SlowAccessMode(const struct mem_controller *ctrl)
 {
 	uint32_t dch;
@@ -2491,6 +2495,7 @@ static void set_SlowAccessMode(const struct mem_controller *ctrl)
 
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
 }
+#endif
 
 /*
 	DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20

src/northbridge/amd/amdk8/raminit_f_dqs.c

@@ -1872,6 +1872,7 @@ static int dqs_load_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
 	return pos;
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
 {
 	/* 30 bytes per channel */
@@ -1902,6 +1903,7 @@ static void dqs_save_MC_NVRAM(unsigned int dev)
 	reg = pci_read_config32(dev, DRAM_CONFIG_HIGH);
 	pos = s3_save_nvram_early(reg, 4, pos);
 }
+#endif
 
 static void dqs_restore_MC_NVRAM(unsigned int dev)
 {

src/northbridge/amd/lx/raminit.c

@@ -35,7 +35,7 @@ static void banner(const char *s)
 	print_debug("======================================\n");
 }
 
-void hcf(void)
+static void hcf(void)
 {
 	print_emerg("DIE\n");
 	/* this guarantees we flush the UART fifos (if any) and also 

src/southbridge/amd/amd8111/amd8111_early_ctrl.c

@@ -35,7 +35,7 @@ static void enable_cf9(void)
 	enable_cf9_x(sbbusn, sbdn);
 }
 
-static void hard_reset(void)
+void hard_reset(void)
 {
         set_bios_reset();
         /* reset */
@@ -68,7 +68,7 @@ static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
 
 }
 
-static void soft_reset(void)
+void soft_reset(void)
 {
 
 	unsigned sblk = get_sblk();

src/southbridge/amd/cs5536/cs5536_ide.c

@@ -46,13 +46,6 @@ static void ide_init(struct device *dev)
 	pci_write_config32(dev, IDE_CFG, ide_cfg);
 }
 
-static void ide_enable(struct device *dev)
-{
-
-	printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);
-
-}
-
 static struct device_operations ide_ops = {
 	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,

src/southbridge/amd/rs780/rs780_early_setup.c

@@ -371,10 +371,9 @@ static void k8_optimization(void)
 #endif	/* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
 
 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1		/* save some spaces */
-void fam10_optimization(void)
+static void fam10_optimization(void)
 {
 	device_t cpu_f0, cpu_f2, cpu_f3;
-	msr_t msr;
 	u32 val;
 
 	printk(BIOS_INFO, "fam10_optimization()\n");
@@ -634,16 +633,16 @@ static void rs780_por_init(device_t nb_dev)
 }
 
 /* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_rs780_dev8()
+static void enable_rs780_dev8(void)
 {
 	set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
 }
 
-static void rs780_before_pci_init()
+static void rs780_before_pci_init(void)
 {
 }
 
-static void rs780_early_setup()
+static void rs780_early_setup(void)
 {
 	device_t nb_dev = PCI_DEV(0, 0, 0);
 	printk(BIOS_INFO, "rs780_early_setup()\n");

src/southbridge/amd/sb700/sb700_smbus.c

@@ -205,7 +205,7 @@ static void alink_ab_indx(u32 reg_space, u32 reg_addr,
 /* space = 0: AX_INDXC, AX_DATAC
  * space = 1: AX_INDXP, AX_DATAP
  */
-static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
 			  u32 mask, u32 val)
 {
 	u32 tmp;

src/southbridge/amd/sb700/sb700_smbus.h

@@ -20,8 +20,6 @@
 #ifndef SB700_SMBUS_H
 #define SB700_SMBUS_H
 
-//#include <stdint.h>
-
 #define SMBHSTSTAT 0x0
 #define SMBSLVSTAT 0x1
 #define SMBHSTCTRL 0x2

src/southbridge/via/vt8237r/vt8237_fadt.c

@@ -51,8 +51,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	memcpy(header->asl_compiler_id, "CORE", 4);
 	header->asl_compiler_revision = 42;
 
-	fadt->firmware_ctrl = facs;
+	fadt->firmware_ctrl = (u32)facs;
-	fadt->dsdt = dsdt;
+	fadt->dsdt = (u32)dsdt;
 	fadt->preferred_pm_profile = 0;
 	fadt->sci_int = 9;
 	fadt->smi_cmd = 0;
@@ -108,9 +108,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	fadt->reset_reg.addrh = 0x0;
 
 	fadt->reset_value = 0;
-	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_l = (u32)facs;
 	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_l = (u32)dsdt;
 	fadt->x_dsdt_h = 0;
 
 	fadt->x_pm1a_evt_blk.space_id = 1;