soc/intel/common: Include Alder Lake-N device IDs

Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs.
Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548)

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Usha P 2022-01-17 20:06:38 +05:30 committed by Felix Held
parent 7760fe4645
commit 8f2df280e1
7 changed files with 26 additions and 0 deletions

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@ -3407,6 +3407,8 @@
#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP8 0x54bf
#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP9 0x54b0
#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP10 0x54b1
#define PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP11 0x54b2
#define PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP12 0x54b3
/* Intel SATA device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00
@ -4022,6 +4024,8 @@
#define PCI_DEVICE_ID_INTEL_ADL_M_ID_2 0x460a
#define PCI_DEVICE_ID_INTEL_ADL_N_ID_1 0x4617
#define PCI_DEVICE_ID_INTEL_ADL_N_ID_2 0x461B
#define PCI_DEVICE_ID_INTEL_ADL_N_ID_3 0x461c
#define PCI_DEVICE_ID_INTEL_ADL_N_ID_4 0x4614
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22
@ -4229,6 +4233,9 @@
#define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4
#define PCI_DEVICE_ID_INTEL_ADP_EMMC 0x54c4
/* Intel UFS device Ids */
#define PCI_DEVICE_ID_INTEL_ADP_UFS 0x54ff
/* Intel Thunderbolt device Ids */
#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP0 0x9a23
#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25
@ -4285,6 +4292,7 @@
#define PCI_DEVICE_ID_INTEL_TGL_H_IPU 0x9a39
#define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19
#define PCI_DEVICE_ID_INTEL_ADL_IPU 0x465d
#define PCI_DEVICE_ID_INTEL_ADL_N_IPU 0x462e
/* Intel Dynamic Tuning Technology Device */
#define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903
@ -4318,6 +4326,10 @@
#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_0 0x43f5
#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_1 0x43f6
#define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_2 0x43f7
#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_0 0x54f0
#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_1 0x54f1
#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_2 0x54f2
#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_3 0x54f3
#define PCI_VENDOR_ID_COMPUTONE 0x8e0e
#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291

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@ -47,6 +47,9 @@ static struct {
{ PCI_DEVICE_ID_INTEL_ADL_M_ID_2, "Alderlake-M" },
{ PCI_DEVICE_ID_INTEL_ADL_N_ID_1, "Alderlake-N" },
{ PCI_DEVICE_ID_INTEL_ADL_N_ID_2, "Alderlake-N" },
{ PCI_DEVICE_ID_INTEL_ADL_N_ID_3, "Alderlake-N" },
{ PCI_DEVICE_ID_INTEL_ADL_N_ID_4, "Alderlake-N" },
};
static struct {

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@ -201,6 +201,8 @@ enum adl_cpu_type get_adl_cpu_type(void)
const uint16_t adl_n_mch_ids[] = {
PCI_DEVICE_ID_INTEL_ADL_N_ID_1,
PCI_DEVICE_ID_INTEL_ADL_N_ID_2,
PCI_DEVICE_ID_INTEL_ADL_N_ID_3,
PCI_DEVICE_ID_INTEL_ADL_N_ID_4,
};
const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),

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@ -39,6 +39,10 @@ static const unsigned short wifi_pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_TGL_H_CNVI_WIFI_1,
PCI_DEVICE_ID_INTEL_TGL_H_CNVI_WIFI_2,
PCI_DEVICE_ID_INTEL_TGL_H_CNVI_WIFI_3,
PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_0,
PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_1,
PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_2,
PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_3,
0
};

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@ -16,6 +16,7 @@ static const uint16_t pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_TGL_H_IPU,
PCI_DEVICE_ID_INTEL_JSL_IPU,
PCI_DEVICE_ID_INTEL_ADL_IPU,
PCI_DEVICE_ID_INTEL_ADL_N_IPU,
0
};

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@ -366,6 +366,8 @@ static const unsigned short pcie_device_ids[] = {
PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP8,
PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP9,
PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP10,
PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP11,
PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP12,
0
};

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@ -438,6 +438,8 @@ static const unsigned short systemagent_ids[] = {
PCI_DEVICE_ID_INTEL_ADL_M_ID_2,
PCI_DEVICE_ID_INTEL_ADL_N_ID_1,
PCI_DEVICE_ID_INTEL_ADL_N_ID_2,
PCI_DEVICE_ID_INTEL_ADL_N_ID_3,
PCI_DEVICE_ID_INTEL_ADL_N_ID_4,
0
};