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soc/amd/picasso: Reduce romstage.c 

Remove the old Stoney Ridge postcar stack frame setup.  Reduce
romstage.c to basic functionality.  Until AGESA's reporting of
memory configuration is available, use the TOM register as an
indicator for the top of usable memory.

Change-Id: I516b79c3e798f5fc68c2771b2f66034c6867b19e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Marshall Dawson 2019-11-17 14:34:52 -07:00
parent badd460229
commit 8f454fd2ea
1 changed files with 14 additions and 44 deletions
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56
src/soc/amd/picasso/romstage.c
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@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@ -14,26 +11,18 @@
* GNU General Public License for more details.
*/
#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <arch/romstage.h>
#include <arch/acpi.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/amd/mtrr.h>
#include <cbmem.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/device.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <elog.h>
#include <soc/northbridge.h>
#include <soc/romstage.h>
#include <soc/southbridge.h>
#include "chip.h"
void __weak mainboard_romstage_entry_s3(int s3_resume)
{
@ -42,52 +31,33 @@ void __weak mainboard_romstage_entry_s3(int s3_resume)
asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
uintptr_t top_of_mem;
int s3_resume;
post_code(0x40);
console_init();
post_code(0x41);
s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
mainboard_romstage_entry_s3(s3_resume);
elog_boot_notify(s3_resume);
if (!s3_resume) {
post_code(0x40);
} else {
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
}
post_code(0x42);
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
post_code(0x43);
top_of_mem = ALIGN_DOWN(rdmsr(TOP_MEM).lo, 8 * MiB);
backup_top_of_low_cacheable(top_of_mem);
post_code(0x44);
if (cbmem_recovery(s3_resume))
printk(BIOS_CRIT, "Failed to recover cbmem\n");
if (romstage_handoff_init(s3_resume))
printk(BIOS_ERR, "Failed to set romstage handoff data\n");
if (CONFIG(SMM_TSEG))
smm_list_regions();
post_code(0x44);
if (postcar_frame_init(&pcf, 1 * KiB))
die("Unable to initialize postcar frame.\n");
/*
* We need to make sure ramstage will be run cached. At this point exact
* location of ramstage in cbmem is not known. Instruct postcar to cache
* 16 megs under cbmem top which is a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t) cbmem_top();
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
/* Cache the TSEG region */
postcar_enable_tseg_cache(&pcf);
post_code(0x45);
run_postcar_phase(&pcf);
run_ramstage();
post_code(0x50); /* Should never see this post code. */
}