mb/google/hatch: Enable console UART

This patch incorporates following changes to enable console on UART0
1. update default console number to 0
2. Enable PCI port for UART0
GPIO configuration will be done by coreboot based on correct console
number.

Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

src/mainboard/google/hatch/Kconfig

@@ -45,6 +45,9 @@ config DIMM_SPD_SIZE
 config DRIVER_TPM_SPI_BUS
 	default 0x1
 
+config UART_FOR_CONSOLE
+	default 0
+
 config GBB_HWID
 	string
 	depends on CHROMEOS

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -85,7 +85,7 @@ chip soc/intel/cannonlake
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1d.4 off end # PCI Express Port 13 (x4)
-		device pci 1e.0 off end # UART #0
+		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 on
 			chip drivers/spi/acpi

src/mainboard/google/hatch/variants/baseboard/gpio.c

@@ -29,6 +29,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* GPP_C11_TP => NC */
+	PAD_NC(GPP_C11, DN_20K),
+	/* GPP_C10_TP => NC */
+	PAD_NC(GPP_C10, DN_20K),
 	/* PCH_I2C_TRACKPAD_SDA */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* PCH_I2C_TRACKPAD_SCL */