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mb/starlabs/lite/{glk/glkr}: Remove unnecessary parameters 

Since using FSP 2.2.0.0, the defaults match the required settings so
they no longer need to be specified.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie0e00cae67cb89b184392e97b8ec196d45ea5d91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2022-05-18 09:16:39 +01:00 committed by Martin L Roth
parent 2d8edebc97
commit 8f5a4d372e
2 changed files with 0 additions and 70 deletions
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30
src/mainboard/starlabs/lite/variants/glk/romstage.c
View File

@ -56,20 +56,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
config->Package = 0x01,
config->Profile = 0x06,
config->MemoryDown = 0x01,
config->DDR3LPageSize = 0x01,
config->DDR3LASR = 0x00,
config->ScramblerSupport = 0x01,
config->ChannelHashMask = 0x36,
config->SliceHashMask = 0x09,
config->InterleavedMode = 0x02,
config->ChannelsSlicesEnable = 0x00,
config->MinRefRate2xEnable = 0x00,
config->DualRankSupportEnable = 0x01,
config->RmtMode = 0x00,
config->MemorySizeLimit = 0x00,
config->LowMemoryMaxValue = 0x00,
config->DisableFastBoot = 0x00,
config->HighMemoryMaxValue = 0x00,
config->DIMM0SPDAddress = 0x00,
config->DIMM1SPDAddress = 0x00,
@ -77,41 +67,21 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
config->Ch0_DeviceWidth = 0x01,
config->Ch0_DramDensity = 0x02,
config->Ch0_Option = 0x03,
config->Ch0_OdtConfig = 0x02,
config->Ch0_TristateClk1 = 0x00,
config->Ch0_Mode2N = 0x00,
config->Ch0_OdtLevels = 0x00,
config->Ch1_RankEnable = 0x03,
config->Ch1_DeviceWidth = 0x01,
config->Ch1_DramDensity = 0x02,
config->Ch1_Option = 0x03,
config->Ch1_OdtConfig = 0x02,
config->Ch1_TristateClk1 = 0x00,
config->Ch1_Mode2N = 0x00,
config->Ch1_OdtLevels = 0x00,
config->Ch2_RankEnable = 0x03,
config->Ch2_DeviceWidth = 0x01,
config->Ch2_DramDensity = 0x02,
config->Ch2_Option = 0x03,
config->Ch2_OdtConfig = 0x00,
config->Ch2_TristateClk1 = 0x00,
config->Ch2_Mode2N = 0x00,
config->Ch2_OdtLevels = 0x00,
config->Ch3_RankEnable = 0x03,
config->Ch3_DeviceWidth = 0x01,
config->Ch3_DramDensity = 0x02,
config->Ch3_Option = 0x03,
config->Ch3_OdtConfig = 0x00,
config->Ch3_TristateClk1 = 0x00,
config->Ch3_Mode2N = 0x00,
config->Ch3_OdtLevels = 0x00,
config->RmtCheckRun = 0x00,
config->RmtMarginCheckScaleHighThreshold = 0x00;
config->MsgLevelMask = 0x00;
memcpy(config->Ch0_Bit_swizzling, &ch0_bit_swizzling,
sizeof(ch0_bit_swizzling));

40
src/mainboard/starlabs/lite/variants/glkr/romstage.c
View File

@ -56,20 +56,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
config->Package = 0x01,
config->Profile = 0x06,
config->MemoryDown = 0x01,
config->DDR3LPageSize = 0x01,
config->DDR3LASR = 0x00,
config->ScramblerSupport = 0x01,
config->ChannelHashMask = 0x36,
config->SliceHashMask = 0x09,
config->InterleavedMode = 0x02,
config->ChannelsSlicesEnable = 0x00,
config->MinRefRate2xEnable = 0x00,
config->DualRankSupportEnable = 0x00,
config->RmtMode = 0x00,
config->MemorySizeLimit = 0x00,
config->LowMemoryMaxValue = 0x00,
config->DisableFastBoot = 0x00,
config->HighMemoryMaxValue = 0x00,
config->DIMM0SPDAddress = 0x00,
config->DIMM1SPDAddress = 0x00,
@ -77,41 +67,11 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
config->Ch0_DeviceWidth = 0x01,
config->Ch0_DramDensity = 0x04,
config->Ch0_Option = 0x03,
config->Ch0_OdtConfig = 0x00,
config->Ch0_TristateClk1 = 0x00,
config->Ch0_Mode2N = 0x00,
config->Ch0_OdtLevels = 0x00,
config->Ch1_RankEnable = 0x03,
config->Ch1_DeviceWidth = 0x01,
config->Ch1_DramDensity = 0x04,
config->Ch1_Option = 0x03,
config->Ch1_OdtConfig = 0x00,
config->Ch1_TristateClk1 = 0x00,
config->Ch1_Mode2N = 0x00,
config->Ch1_OdtLevels = 0x00,
config->Ch2_RankEnable = 0x00,
config->Ch2_DeviceWidth = 0x00,
config->Ch2_DramDensity = 0x00,
config->Ch2_Option = 0x00,
config->Ch2_OdtConfig = 0x00,
config->Ch2_TristateClk1 = 0x00,
config->Ch2_Mode2N = 0x00,
config->Ch2_OdtLevels = 0x00,
config->Ch3_RankEnable = 0x00,
config->Ch3_DeviceWidth = 0x00,
config->Ch3_DramDensity = 0x00,
config->Ch3_Option = 0x00,
config->Ch3_OdtConfig = 0x00,
config->Ch3_TristateClk1 = 0x00,
config->Ch3_Mode2N = 0x00,
config->Ch3_OdtLevels = 0x00,
config->RmtCheckRun = 0x00,
config->RmtMarginCheckScaleHighThreshold = 0x00,
config->MsgLevelMask = 0x00,
memcpy(config->Ch0_Bit_swizzling, &ch0_bit_swizzling,
sizeof(ch0_bit_swizzling));